Real-Time FPGA-Based Detection of Speeded-Up Robust Features Using Separable Convolution
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DOI: 10.1109/tii.2017.2764485
Abstract: In this paper, we propose a novel architecture for efficient detection of speeded-up robust features (SURF) for field-programmable gate array (FPGA). The main benefits of the proposed architecture are in real-time low-latency performance and scalability.… read more here.
Keywords: detection; real time; speeded robust; inline formula ... See more keywords