DFF Layout Variations in CMOS SOI—Analysis of Hardening by Design Options
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DOI: 10.1109/tns.2020.2973569
Abstract: Four D flip-flop (DFF) layouts were created from the same schematic in Sandia National Laboratories’ CMOS7 silicon-on-insulator (SOI) process. Single-event upset (SEU) modeling and testing showed an improved response with the use of shallow (not… read more here.
Keywords: soi analysis; dff layout; variations cmos; layout variations ... See more keywords