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Published in 2025 at "IEEE Transactions on Circuits and Systems II: Express Briefs"
DOI: 10.1109/tcsii.2025.3571482
Abstract: We propose a technique able to reduce nonlinearity in multiplexer-based digital delay interpolators, by optimizing transistor sizing. In our approach, we adjust the driving capabilities of each MOSFET within multiplexers to minimize the interpolation error,…
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Keywords:
delay interpolators;
transistor sizing;
digital delay;
based digital ... See more keywords