Radiation Hardened Latch Designs for Double and Triple Node Upsets
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DOI: 10.1109/tetc.2017.2776285
Abstract: As the process feature size continues to scale down, the susceptibility of logic circuits to radiation induced error has increased. This trend has led to the increase in sensitivity of circuits to multi-node upsets. Previously,… read more here.
Keywords: dnu tolerant; tolerant latch; triple node; node upsets ... See more keywords