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Published in 2017 at "IEEE Computer Architecture Letters"
DOI: 10.1109/lca.2017.2654347
Abstract: Server workloads frequently encounter L1-D cache misses, and hence, lose significant performance potential. One way to reduce the number of L1-D misses or their effect is data prefetching. As L1-D access sequences have high temporal…
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Keywords:
temporal data;
domino;
domino prefetcher;
efficient temporal ... See more keywords