A Bottom-Gate Metal–Oxide Thin-Film Transistor With Self-Aligned Source/Drain Regions
Sign Up to like & getrecommendations! Published in 2018 at "IEEE Transactions on Electron Devices"
DOI: 10.1109/ted.2018.2833057
Abstract: Proper driving of a large-area, high-resolution, and high-frame-rate active-matrix display can be hindered by excessive delay along a signal path, such as a scan line. Depending on the transistor architecture, such delay could be dominated… read more here.
Keywords: drain regions; bottom gate; self aligned; gate ... See more keywords
Improving ESD Protection Robustness Using SiGe Source/Drain Regions in Tunnel FET
Sign Up to like & getrecommendations! Published in 2018 at "Micromachines"
DOI: 10.3390/mi9120657
Abstract: Currently, a tunnel field-effect transistor (TFET) is being considered as a suitable electrostatic discharge (ESD) protection device in advanced technology. In addition, silicon-germanium (SiGe) engineering is shown to improve the performance of TFET-based ESD protection… read more here.
Keywords: drain regions; esd protection; source drain; tfet ... See more keywords