Articles with "dram" as a keyword



True Nonvolatile High‐Speed DRAM Cells Using Tailored Ultrathin IGZO

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Published in 2023 at "Advanced Materials"

DOI: 10.1002/adma.202210554

Abstract: Severe power consumption in the continuous scaling of Silicon‐based dynamic random access memory (DRAM) technology quests for a transistor technology with a much lower off‐state leakage current. Wide bandgap amorphous oxide semiconductors, especially indium‐gallium‐zinc‐oxide (IGZO)… read more here.

Keywords: high speed; speed dram; true nonvolatile; dram ... See more keywords

Task‐aware swapping for efficient DNN inference on DRAM‐constrained edge systems

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Published in 2022 at "International Journal of Intelligent Systems"

DOI: 10.1002/int.22933

Abstract: Object detection at the edge side is a common task in various environments. The deployment of convolutional neural networks in intelligent edge systems is very challenging because of the highly constrained main‐memory space. This study… read more here.

Keywords: systems task; edge systems; task; task aware ... See more keywords

Ultra-low power 1T-DRAM in FDSOI technology

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Published in 2017 at "Microelectronic Engineering"

DOI: 10.1016/j.mee.2017.05.047

Abstract: A systematic study of a capacitorless 1T-DRAM fabricated in 28nm FDSOI technology is presented. The operation mechanism is based on band modulation. The Z2-FET memory cell features a large current sense margin and small OFF-state… read more here.

Keywords: fdsoi technology; power; dram; low power ... See more keywords

Translation, Cross-cultural Adaptation and Reliability of Brazilian portuguese version of the DRAM Questionnaire for Psychometric Evaluation in Low Back Pain ∗

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Published in 2020 at "Revista Brasileira de Ortopedia"

DOI: 10.1055/s-0039-1700812

Abstract: Objective  Based on studies regarding pain physiology and its relation to emotional distress conditions, psychological evaluation became essential to determine the most favorable patient profiles to distinct therapeutic approaches. The Distress Risk Assessment Method (DRAM)… read more here.

Keywords: brazilian portuguese; dram; portuguese version; version dram ... See more keywords

kb_DRAM: annotation and metabolic profiling of genomes with DRAM in KBase

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Published in 2022 at "Bioinformatics"

DOI: 10.1093/bioinformatics/btad110

Abstract: Summary Annotation is predicting the location of and assigning function to genes in a genome. DRAM is a tool developed to annotate bacterial, archaeal and viral genomes derived from pure cultures or metagenomes. DRAM distills… read more here.

Keywords: dram; annotation metabolic; metabolic profiling; kbase ... See more keywords
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DRAM for distilling microbial metabolism to automate the curation of microbiome function

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Published in 2020 at "Nucleic Acids Research"

DOI: 10.1093/nar/gkaa621

Abstract: Abstract Microbial and viral communities transform the chemistry of Earth's ecosystems, yet the specific reactions catalyzed by these biological engines are hard to decode due to the absence of a scalable, metabolically resolved, annotation software.… read more here.

Keywords: metabolism; dram distilling; microbiome function; dram ... See more keywords

Polycrystalline-Silicon-MOSFET-Based Capacitorless DRAM With Grain Boundaries and Its Performances

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Published in 2021 at "IEEE Access"

DOI: 10.1109/access.2021.3068987

Abstract: In this work, a capacitorless one-transistor dynamic random access memory (1T-DRAM) based on a polycrystalline silicon (poly-Si) metal–oxide–semiconductor field-effect transistor was designed and analyzed through a technology computer-aided design (TCAD) simulation. A poly-Si thin film… read more here.

Keywords: tex math; dram; grain boundaries; inline formula ... See more keywords

A Hybrid Low-Dropout (LDO) Regulator Using a Load Replication Circuit for DRAM Cores

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Published in 2022 at "IEEE Access"

DOI: 10.1109/access.2022.3223135

Abstract: This paper presents a cost-effective hybrid low drop-out regulator (LDO) circuitry for state-of-the-art DDR DRAM cores that not only supports various refresh operations, but also meets the JEDEC specification of the refresh period by improving… read more here.

Keywords: load replication; dram cores; replication circuit; inline formula ... See more keywords

ZEC ECC: A Zero-Byte Eliminating Compression-Based ECC Scheme for DRAM Reliability

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Published in 2024 at "IEEE Access"

DOI: 10.1109/access.2024.3431209

Abstract: As DRAM cells continue to shrink, the conventional single error correction and double error detection (SECDED) code is not sufficient to provide DRAM error resilience. To satisfy DRAM reliability demands, various studies have proposed multi-bit… read more here.

Keywords: zero byte; dram; ecc; compression ... See more keywords

A Highly Parallel DRAM Architecture to Mitigate Large Access Latency and Improve Energy Efficiency of Modern DRAM Systems

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Published in 2024 at "IEEE Access"

DOI: 10.1109/access.2024.3512176

Abstract: Modern Dynamic Random Access Memory (DRAM) banks are characterized by their ability to work in parallel, enabling concurrent servicing of multiple memory accesses through the interleaved DRAM banks. This attractive feature is supported in modern… read more here.

Keywords: energy; dram; access; dram architecture ... See more keywords

An Innovative Indicator to Evaluate DRAM Cell Transistor Leakage Current Distribution

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Published in 2018 at "IEEE Journal of the Electron Devices Society"

DOI: 10.1109/jeds.2017.2758026

Abstract: This paper is the first to propose an innovative method for measuring variations in dynamic random access memory (DRAM) cell transistors. Structural dispersion induces an extremely high cell leakage current, which determines aspects of DRAM… read more here.

Keywords: cell leakage; leakage; dram; distribution ... See more keywords