Construction of Cyclic Redundancy Check Codes for SDDC Decoding in DRAM Systems
Sign Up to like & getrecommendations! Published in 2023 at "IEEE Transactions on Circuits and Systems II: Express Briefs"
DOI: 10.1109/tcsii.2022.3175066
Abstract: Single device data correction (SDDC) is a main reliability, availability, and serviceability feature of DRAM systems in servers due to the significant hard-failure rate associated with DRAM devices. To correct errors in one DRAM device,… read more here.
Keywords: cyclic redundancy; redundancy check; error; sddc decoding ... See more keywords
Vertically Replaceable Memory Block Architecture for Stacked DRAM Systems by Wafer-on-Wafer (WOW) Technology
Sign Up to like & getrecommendations! Published in 2020 at "IEEE Transactions on Electron Devices"
DOI: 10.1109/ted.2020.3010894
Abstract: This article proposes a 3-D-based redundancy scheme for the stacked dynamic random-access memory (DRAM) systems, which enables highly efficient productivity with the wafer-on-wafer (WOW) technology. Vertically replaceable block scheme and redundantly added wafer stack(s) are… read more here.
Keywords: dram systems; memory; technology; wafer wafer ... See more keywords