Improving the performance of dual-k spacer underlap Double Gate TFET
Sign Up to like & getrecommendations! Published in 2018 at "Superlattices and Microstructures"
DOI: 10.1016/j.spmi.2018.10.006
Abstract: Abstract In this paper, the effect of dual-k spacer is investigated on underlap Double-Gate TFET (DGTFET) for low-k and high-k gate dielectrics. Simulation study shows that the position of dual-k spacer junction must be aligned… read more here.
Keywords: double gate; gate; dual spacer; underlap double ... See more keywords
Impact of varying carbon concentration in SiC S/D asymmetric dual-k spacer for high performance and reliable FinFET
Sign Up to like & getrecommendations! Published in 2018 at "Journal of Semiconductors"
DOI: 10.1088/1674-4926/39/10/104001
Abstract: We propose a reliable asymmetric dual-k spacer with SiC source/drain (S/D) pocket as a stressor for a Si channel. This enhances the device performance in terms of electron mobility (eMobility), current driving capabilities, transconductance (Gm)… read more here.
Keywords: impact varying; varying carbon; dual spacer; asymmetric dual ... See more keywords
Spacer Engineering on Nanosheet Field Effect Transistor towards Device and Circuit Perspective
Sign Up to like & getrecommendations! Published in 2023 at "ECS Journal of Solid State Science and Technology"
DOI: 10.1149/2162-8777/acd65e
Abstract: For the first time, a nanosheet field effect transistor (NS FET) performance is demonstrated by incorporating various device engineering at both device and circuit levels. Various device topologies like lightly-doped drain/source, underlap, single and dual-k… read more here.
Keywords: circuit; spacer; dual spacer; fet ... See more keywords