A 12-bit 120-MS/s SAR ADC with improved split capacitive DAC and low-noise dynamic comparator
Sign Up to like & getrecommendations! Published in 2020 at "Analog Integrated Circuits and Signal Processing"
DOI: 10.1007/s10470-019-01581-0
Abstract: This paper presents a 12-bit 120-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) with improved split capacitive DAC and low-noise dynamic comparator. A split DAC structure with parasitic capacitance depressed technique is introduced, the top-plate… read more here.
Keywords: dac; adc improved; comparator; dynamic comparator ... See more keywords