A Dynamic Leakage and Slew Rate Compensation Circuit for 40-nm CMOS Mixed-Voltage Output Buffer
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DOI: 10.1109/tvlsi.2017.2736782
Abstract: This paper proposes a 40-nm CMOS $2 \times {\mathrm{ VDD}}$ buffer with slew rate (SR) variation compensated and dynamic leakage reduction during signal transitions. By using the dual variation detectors, five process corners for both… read more here.
Keywords: tex math; slew rate; dynamic leakage; inline formula ... See more keywords