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Efficient Memory Partitioning for Parallel Data Access in FPGA via Data Reuse

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1 Published in 2017 at "IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"

DOI: 10.1109/tcad.2017.2648838

Abstract: Parallelizing the memory accesses in a nested loop is a critical challenge to facilitate loop pipelining. An effective approach for high-level synthesis on field-programmable gate array is to map these accesses to multiple on-chip memory… read more here.

Keywords: data access; memory partitioning; parallel data; efficient memory ... See more keywords