An Area-Efficient TMR Architecture Inspired From Fast FIR Algorithm for Fault Tolerance
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DOI: 10.1109/access.2024.3505916
Abstract: High-end commercial silicon chips used in aerospace and other industries utilize technology nodes at deep sub-micron levels. Efforts are underway to assess the feasibility of integrating even smaller nano-scale devices for secure communication, high-speed computing,… read more here.
Keywords: fir; architecture; efficient tmr; area ... See more keywords