A power-efficient variable-length prime factor MDC FFT architecture for high-speed wireless communication applications
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DOI: 10.1016/j.aeue.2020.153194
Abstract: Abstract In this paper, a variable-size power-efficient two-parallel prime factor MDC FFT architecture is proposed which uses a novel reconfigurable processing element pair (RPEP). The prior reconfigurable FFT approaches merely concentrate on FFT architectures with… read more here.
Keywords: fft; power; factor mdc; power efficient ... See more keywords