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Published in 2020 at "Circuits, Systems, and Signal Processing"
DOI: 10.1007/s00034-019-01230-x
Abstract: This paper presents a new fast-lock all-digital delay-locked loop (DLL) for next-generation memory devices such as DDR5 SDRAMs. The proposed DLL utilizes a new two-step time-to-digital converter (TDC)-based phase detecting and tracking scheme that results…
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Keywords:
two step;
time;
ghz;
dll ... See more keywords
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Published in 2022 at "IEEE Access"
DOI: 10.1109/access.2022.3224451
Abstract: An all-digital clock frequency multiplier that achieves excellent locking time for an energy-efficient chiplet-based system-on-chip (SoC) design is presented. The proposed architecture is based on an all-digital multiplying delay-locked loop (MDLL) to provide fast locking…
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Keywords:
digital clock;
efficient chiplet;
time;
fast lock ... See more keywords