Reconfigurable VLSI design of a changeable hybrid-radix FFT hardware architecture with 2D-FIFO storing structure for 3GPP LTE systems
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DOI: 10.1016/j.icte.2017.11.007
Abstract: Abstract This paper presents a reconfigurable Fast Fourier Transform (FFT) hardware architecture for 3GPP LTE systems. In the main FFT computing process, a novel processing kernel engine is proposed to support four configuration types of… read more here.
Keywords: fft; 3gpp lte; changeable hybrid; hardware architecture ... See more keywords
Optimum MDC FFT Hardware Architectures in Terms of Delays and Multiplexers
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DOI: 10.1109/tcsii.2020.3022528
Abstract: In this brief, we show how to derive all the optimum multi-path delay commutator (MDC) fast Fourier transform (FFT) hardware architectures in terms of delays and multiplexers and calculate the number of such architectures. The… read more here.
Keywords: number; delays multiplexers; fft hardware; hardware architectures ... See more keywords
A Variable-Size FFT Hardware Accelerator Based on Matrix Transposition
Sign Up to like & getrecommendations! Published in 2018 at "IEEE Transactions on Very Large Scale Integration (VLSI) Systems"
DOI: 10.1109/tvlsi.2018.2846688
Abstract: Fast Fourier transform (FFT) is the kernel and the most time-consuming algorithm in the domain of digital signal processing, and the FFT sizes of different applications are very different. Therefore, this paper proposes a variable-size… read more here.
Keywords: size; fft hardware; fft; hardware accelerator ... See more keywords