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   Articles with "finfet" as a keyword



Gate and drain SEU sensitivity of sub-20-nm FinFET- and Junctionless FinFET-based 6T-SRAM circuits by 3D TCAD simulation

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recommendations! Published in 2017 at "Journal of Computational Electronics"

DOI: 10.1007/s10825-016-0950-y

Abstract: Scaling of metal–oxide–semiconductor field-effect transistors (MOSFETs) to below a few tens of nanometer has failed to make significant improvements. FinFETs were introduced to replace MOS devices in circuits, offering good performance improvement in the nanoscale… read more here.

Keywords: junctionless finfet; based sram; finfet junctionless; finfet ... See more keywords

Comparative analysis of the quantum FinFET and trigate FinFET based on modeling and simulation

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recommendations! Published in 2019 at "Journal of Computational Electronics"

DOI: 10.1007/s10825-018-01294-z

Abstract: A comparative analysis of the trigate fin-shaped field-effect transistor (FinFET) and quantum FinFET (QFinFET) is carried out by using density gradient quantization models in the Synopsys three-dimensional (3-D) technology computer-aided design (TCAD) platform. The gate… read more here.

Keywords: quantum finfet; trigate finfet; comparative analysis; finfet ... See more keywords

Design and structural optimization of junctionless FinFET with Gaussian-doped channel

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recommendations! Published in 2018 at "Journal of Computational Electronics"

DOI: 10.1007/s10825-018-1131-y

Abstract: A junctionless (JL) fin field-effect transistor (FinFET) structure with a Gaussian doping distribution, named the Gaussian-channel junctionless FinFET, is presented. The structure has a nonuniform doping distribution across the device layer and is designed with… read more here.

Keywords: design structural; junctionless; junctionless finfet; structure ... See more keywords
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Comparative performance of the ultra-short channel technology for the DG-FinFET characteristics using different high-k dielectric materials

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recommendations! Published in 2020 at "Indian Journal of Physics"

DOI: 10.1007/s12648-020-01846-9

Abstract: The downscaling of the SOI-MOSFET device has an important role of the advanced technology in the semiconductor industry, so the researchers aim to find the structure which can improve the considerable reduction, this paper is investigated… read more here.

Keywords: using different; different high; ultra short; technology ... See more keywords

Power reduction for recovery of a FinFET by electrothermal annealing

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recommendations! Published in 2019 at "Solid-State Electronics"

DOI: 10.1016/j.sse.2018.10.008

Abstract: Abstract A strategy of reducing the power consumption to cure gate dielectric damage by electrothermal annealing (ETA) is proposed. A tri-gate FinFET was fabricated to demonstrate the damage curing by the ETA. Localized Joule heat… read more here.

Keywords: power reduction; power consumption; power; gate ... See more keywords

Quantitative Electron Energy Loss Spectroscopy (EELS) Analysis of Flowable CVD Oxide for Shallow Trench Isolation of finFET Integration

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recommendations! Published in 2017 at "Microscopy and Microanalysis"

DOI: 10.1017/s1431927617007978

Abstract: Non-planar semiconductor devices, such asvertical f in-based field-effect transistor (finFET) device, h ave become a viable technology for 22nm node and beyond [1-4]. However, finFET device fabrication faces new challenges and process variation control become… read more here.

Keywords: integration; shallow trench; finfet; spectroscopy ... See more keywords

Study on the regulation factors and mechanism of self-heating effects in non-rectangular 14 nm bulk FinFET

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recommendations! Published in 2024 at "Semiconductor Science and Technology"

DOI: 10.1088/1361-6641/ad689f

Abstract: This work investigates the innovative design of a 14 nm bulk 3D non-rectangular structure fin field-effect transistor (FinFET). By incorporating a cylindrical trapezoidal structure into the upper portion of the FinFET, it transcend the limitations… read more here.

Keywords: self heating; effect; non rectangular; finfet ... See more keywords

A Cryo-CMOS Low-Power Semi-Autonomous Transmon Qubit State Controller in 14-nm FinFET Technology

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recommendations! Published in 2022 at "IEEE Journal of Solid-State Circuits"

DOI: 10.1109/jssc.2022.3201775

Abstract: A scalable, non-multiplexed cryogenic 14-nm FinFET quantum bit (qubit) state controller (QSC) for use in the semi-autonomous control of superconducting transmon qubits is reported. The QSC includes an augmented general-purpose digital processor that supports waveform… read more here.

Keywords: inline formula; power; finfet; tex math ... See more keywords

A Fully Integrated 160-Gb/s D-Band Transmitter Achieving 1.1-pJ/b Efficiency in 22-nm FinFET

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recommendations! Published in 2022 at "IEEE Journal of Solid-State Circuits"

DOI: 10.1109/jssc.2022.3208510

Abstract: This work presents a fully integrated 140-GHz transmitter (TX) achieving a data rate of 160 Gb/s with ~1-pJ/b efficiency in the 22-nm Intel FinFET technology. The TX leverages a wideband radio frequency digital to analog… read more here.

Keywords: fully integrated; 160 band; integrated 160; transmitter achieving ... See more keywords

Negative Capacitance FinFET With Sub-20-mV/decade Subthreshold Slope and Minimal Hysteresis of 0.48 V

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recommendations! Published in 2017 at "IEEE Electron Device Letters"

DOI: 10.1109/led.2017.2672967

Abstract: In this letter, an n-type short-channel negative capacitance FinFET (NC-FinFET) with a hysteresis window of 0.48 V, an on-/off-current ratio of 107, and a sub-20-mV/decade average subthreshold slope (SSavg) that is intended to overcome the… read more here.

Keywords: hysteresis; sub; finfet; tex math ... See more keywords

Spacer Engineering in Negative Capacitance FinFETs

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recommendations! Published in 2019 at "IEEE Electron Device Letters"

DOI: 10.1109/led.2019.2911104

Abstract: The spacer design of the negative-capacitance FinFET (NC-FinFET) is investigated by using Sentaurus technology computer-aided design (TCAD). The spacer affects not only the gate capacitance but also the drain current due to the additional gate… read more here.

Keywords: spacer engineering; finfet; negative capacitance; spacer ... See more keywords