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Published in 2024 at "Electronics Letters"
DOI: 10.1049/ell2.13111
Abstract: This paper proposes a simple yet effective scheme for NAND Flash memories that employ on‐chip microcontroller units (MCUs) to manage internal array operations. Through minimal hardware overhead, the proposed scheme enables—without mask revision— executing new…
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Keywords:
nand flash;
flash memories;
buffer data;
chip ... See more keywords
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Published in 2018 at "AIP Advances"
DOI: 10.1063/1.5017945
Abstract: This paper presents a neutron accelerated study of soft errors in advanced electronic devices used in space missions, i.e. Flash memories performed at the ChipIr and VESUVIO beam lines at the ISIS spallation neutron source.…
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Keywords:
neutron;
space;
flash memories;
isis spallation ... See more keywords
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Published in 2019 at "IEEE Journal of Solid-State Circuits"
DOI: 10.1109/jssc.2018.2884949
Abstract: Adaptive artificial neural network (ANN)-coupled low-density parity-check (LDPC) error-correcting code (ECC) (ANN-LDPC ECC) is proposed to increase acceptable errors for various NAND flash memories. The proposed ANN-LDPC ECC can be the universal solutions for 3-D…
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Keywords:
ldpc;
ann ldpc;
charge trap;
floating gate ... See more keywords
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Published in 2024 at "IEEE Transactions on Electron Devices"
DOI: 10.1109/ted.2024.3400757
Abstract: In this article, a time constant of lateral charge loss (LCL) mechanism inside 3-D NAND flash memories during their data retention process is comprehensively investigated. 1-D multiscale simulation is conducted to investigate the lateral migration…
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Keywords:
time;
charge loss;
nand flash;
flash memories ... See more keywords