Low power and high-speed FPGA implementation for 4D memristor chaotic system for image encryption
Sign Up to like & getrecommendations! Published in 2020 at "Multimedia Tools and Applications"
DOI: 10.1007/s11042-019-08517-w
Abstract: In this paper, we proposed a novel low power and high-speed FPGA implementation of the 4D memristor chaotic system with cubic nonlinearity based on Xilinx System Generator (XSG) model. Firstly, a pseudo-random number generator based… read more here.
Keywords: memristor; chaotic system; memristor chaotic; fpga implementation ... See more keywords
Triple frame buffer FPGA implementation
Sign Up to like & getrecommendations! Published in 2019 at "HardwareX"
DOI: 10.1016/j.ohx.2019.e00064
Abstract: Abstract This article demonstrates a Verilog-based triple frame buffer capable of buffering arbitrary data, such as camera frames, between any two asynchronous processes. The frame buffer modules consume 143 logic elements and use a simple,… read more here.
Keywords: frame buffer; fpga implementation; triple frame; buffer fpga ... See more keywords
FPGA implementation of hardware architecture with AES encryptor using sub-pipelined S-box techniques for compact applications
Sign Up to like & getrecommendations! Published in 2020 at "Automatika"
DOI: 10.1080/00051144.2020.1816388
Abstract: Advanced Encryption Standard (AES) is a thriving cryptographic algorithm that can be utilized to guarantee security in electronic information. It remains to uphold to be resistive from most of the attacks. In this work, AES-128… read more here.
Keywords: implementation hardware; fpga implementation; encryption; box ... See more keywords
FPGA Implementation for Balise Telegram Decoding and Field Test Validation
Sign Up to like & getrecommendations! Published in 2022 at "IEEE Intelligent Transportation Systems Magazine"
DOI: 10.1109/mits.2019.2953541
Abstract: In many countries’ railway systems, the European Railway Traffic Management System/European Train Control System (ERTMS/ETCS) is used to detect the exact location of a train on a running train. ETCS uses balises to transmit position… read more here.
Keywords: balise telegram; decoding field; telegram decoding; fpga implementation ... See more keywords
FPGA Implementation of Threshold-Type Binary Memristor and Its Application in Logic Circuit Design
Sign Up to like & getrecommendations! Published in 2021 at "Micromachines"
DOI: 10.3390/mi12111344
Abstract: In this paper, a memristor model based on FPGA (field programmable gate array) is proposed, by using which the circuit of AND gate and OR gate composed of memristors is built. Combined with the original… read more here.
Keywords: gate; circuit; fpga implementation; implementation threshold ... See more keywords
Efficient FPGA Implementation of High-Throughput Mixed Radix Multipath Delay Commutator FFT Processor for MIMO-OFDM
Sign Up to like & getrecommendations! Published in 2017 at "Advances in Electrical and Computer Engineering"
DOI: 10.4316/aece.2017.01005
Abstract: This article presents and evaluates pipelined architecture designs for an improved high-frequency Fast Fourier Transform (FFT) processor implemented on Field Programmable Gate Arrays ( ... read more here.
Keywords: efficient fpga; fft; fpga implementation; implementation high ... See more keywords