Input frequency and the acquisition of syllable structure in Polish
Sign Up to like & getrecommendations! Published in 2017 at "Language Acquisition"
DOI: 10.1080/10489223.2016.1179743
Abstract: ABSTRACT This article examines phonological development and its relationship to input statistics. Using novel data from a longitudinal corpus of spontaneous child speech in Polish, we evaluate and compare the predictions of a variety of… read more here.
Keywords: input frequency; input; frequency acquisition; syllable structure ... See more keywords
A Sub-0.25-pJ/bit 47.6-to-58.8-Gb/s Reference-Less FD-Less Single-Loop PAM-4 Bang-Bang CDR With a Deliberate-Current-Mismatch Frequency Acquisition Technique in 28-nm CMOS
Sign Up to like & getrecommendations! Published in 2022 at "IEEE Journal of Solid-State Circuits"
DOI: 10.1109/jssc.2022.3140778
Abstract: This article reports a half-rate single-loop bang-bang clock and data recovery (BBCDR) circuit without the need of reference and frequency detector (FD). Specifically, we propose a deliberate-current-mismatch charge-pump pair to enable fast and robust frequency… read more here.
Keywords: bang bang; frequency; frequency acquisition; single loop ... See more keywords
A 0.32–2.7 Gb/s Reference-Less Continuous-Rate Clock and Data Recovery Circuit With Unrestricted and Fast Frequency Acquisition
Sign Up to like & getrecommendations! Published in 2021 at "IEEE Transactions on Circuits and Systems II: Express Briefs"
DOI: 10.1109/tcsii.2021.3053581
Abstract: This brief presents a design of fast frequency locking 320 Mb/s to 2.7 Gb/s continuous-rate reference-less clock and data recovery (CDR) circuit. A simultaneous coarse/fine frequency acquisition processes are being done to achieve an unrestricted… read more here.
Keywords: clock data; frequency; rate; fast frequency ... See more keywords