Practical Full Chip Clock Distribution Design With a Flexible Topology and Hybrid Metaheuristic Technique
Sign Up to like & getrecommendations! Published in 2021 at "IEEE Access"
DOI: 10.1109/access.2021.3053052
Abstract: This article recommends a practical technique to design full chip (FC) clock tree of a complex system-on-chip (SoC). In the new business environment, the market prefers a highly integrated but low power SoC with fast… read more here.
Keywords: chip clock; topology; clock; full chip ... See more keywords
A Fast Leakage-Aware Full-Chip Transient Thermal Estimation Method
Sign Up to like & getrecommendations! Published in 2018 at "IEEE Transactions on Computers"
DOI: 10.1109/tc.2017.2778066
Abstract: Accurate and fast thermal estimation is important for the runtime thermal regulation of modern microprocessors due to excessive on-chip temperatures. However, due to the nonlinear relationship between the leakage power and temperature, full-chip thermal estimation… read more here.
Keywords: estimation; thermal estimation; leakage; full chip ... See more keywords
Real-Time Full-Chip Thermal Tracking: A Post-Silicon, Machine Learning Perspective
Sign Up to like & getrecommendations! Published in 2022 at "IEEE Transactions on Computers"
DOI: 10.1109/tc.2021.3086112
Abstract: In this article, we present a novel approach to real-time tracking of full-chip heatmaps for commercial off-the-shelf microprocessors based on machine-learning. The proposed post-silicon approach, named RealMaps, only uses the existing embedded temperature sensors and… read more here.
Keywords: full chip; mml; real time; chip ... See more keywords
DAMO: Deep Agile Mask Optimization for Full-Chip Scale
Sign Up to like & getrecommendations! Published in 2022 at "IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"
DOI: 10.1109/tcad.2021.3116511
Abstract: Continuous scaling of the very-large-scale integration system leaves a significant challenge on manufacturing; thus optical proximity correction (OPC) is widely applied in conventional design flow for manufacturability optimization. Traditional techniques conduct OPC by leveraging a… read more here.
Keywords: full chip; chip scale; mask optimization; chip ... See more keywords
GridNetOpt: Fast Full-Chip EM-Aware Power Grid Optimization Accelerated by Deep Neural Networks
Sign Up to like & getrecommendations! Published in 2023 at "IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"
DOI: 10.1109/tcad.2022.3206397
Abstract: This article presents a fast full-chip electromigration (EM) aware IR drop constrained optimization framework, named GridNetOpt, for on-chip power grid networks accelerated by deep neural networks (DNNs). Compared to the existing linear programming-based methods, the… read more here.
Keywords: full chip; power grid; power; optimization ... See more keywords
Complementary FET (CFET) Standard Cell Design for Low Parasitics and Its Impact on VLSI Prediction at 3-nm Process
Sign Up to like & getrecommendations! Published in 2023 at "IEEE Transactions on Very Large Scale Integration (VLSI) Systems"
DOI: 10.1109/tvlsi.2022.3220339
Abstract: Complementary field-effect transistor (CFET) is a future transistor type with a high potential to be used beyond 3-nm technology nodes. Despite its high future value, studies related to CFETs mostly focused on the device aspects.… read more here.
Keywords: full chip; complementary fet; vlsi; design ... See more keywords