Articles with "fused multiply" as a keyword



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Vector Processing-Aware Advanced Clock-Gating Techniques for Low-Power Fused Multiply-Add

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Published in 2018 at "IEEE Transactions on Very Large Scale Integration (VLSI) Systems"

DOI: 10.1109/tvlsi.2017.2784807

Abstract: The need for power efficiency is driving a rethink of design decisions in processor architectures. While vector processors succeeded in the high-performance market in the past, they need a retailoring for the mobile market that… read more here.

Keywords: vector; gating techniques; clock gating; power ... See more keywords