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Published in 2018 at "IEEE Journal of Solid-State Circuits"
DOI: 10.1109/jssc.2018.2875106
Abstract: This paper presents a fully integrated shunt-based current sensor that supports a 25-V input common-mode range while operating from a single 1.5-V supply. It uses a high-voltage beyond-the-rails ADC to directly digitize the voltage across…
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Keywords:
current sensor;
compensation;
sensor;
gain error ... See more keywords
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Published in 2020 at "IEEE Journal of Solid-State Circuits"
DOI: 10.1109/jssc.2019.2962140
Abstract: This article presents an interstage gain error shaping (GES) technique that can substantially suppress the in-band quantization leakage error caused by the interstage gain error in pipeline analog-to-digital converters (ADCs). It works for both closed-loop…
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Keywords:
gain error;
error;
interstage gain;
error shaping ... See more keywords
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Published in 2021 at "IEEE Journal of Solid-State Circuits"
DOI: 10.1109/jssc.2021.3111912
Abstract: This article presents an inherent gain error-tolerant noise-shaping (NS) successive approximation register (SAR)-assisted pipelined analog-to-digital converter (ADC). The architecture is hybrid with a pure passive-feedforward (FF) NS SAR ADC in the first stage of the…
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Keywords:
gain error;
error;
adc;
gain ... See more keywords
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Published in 2024 at "IEEE Transactions on Circuits and Systems II: Express Briefs"
DOI: 10.1109/tcsii.2023.3296453
Abstract: This brief presents a 70.6-dB SNDR pipeline-successive approximation register (SAR) analog-to-digital converter (ADC) that utilizes an Adaptive-Region-Selection (ARS) technique to linearize the residue amplification. The proposed technique avoids the complex high-order nonlinearity detection and correction…
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Keywords:
gain error;
adaptive region;
pipeline;
sar ... See more keywords