Characterization of charge trapping mechanisms in GaN vertical Fin FETs under positive gate bias
Sign Up to like & getrecommendations! Published in 2019 at "Microelectronics Reliability"
DOI: 10.1016/j.microrel.2019.113488
Abstract: Abstract In this paper, we present a comprehensive analysis of the charge trapping mechanisms that affect the GaN based vertical Fin FETs when the devices are submitted to positive gate bias. Devices with higher channel… read more here.
Keywords: gate bias; trapping mechanisms; charge trapping; gate ... See more keywords
Gate Bias Stress Instability and Hysteresis Characteristics of InAs Nanowire Field-Effect Transistors.
Sign Up to like & getrecommendations! Published in 2020 at "ACS applied materials & interfaces"
DOI: 10.1021/acsami.0c17317
Abstract: Because of the excellent electrical properties, III-V semiconductor nanowires are promising building blocks for next-generation electronics; however, their rich surface states inevitably contribute large amounts of charge traps, leading to gate bias stress instability and… read more here.
Keywords: stress instability; gate bias; hysteresis; bias stress ... See more keywords
Comparison between nMOS and pMOS Ω-gate nanowire down to 10 nm width as a function of back gate bias
Sign Up to like & getrecommendations! Published in 2019 at "Semiconductor Science and Technology"
DOI: 10.1088/1361-6641/aafccc
Abstract: This paper presents a comparison between nMOS and pMOS Omega-Gate Nanowire for different channel width (W-NW) down to 10 nm as a function of the large back gate bias variation (from +20 to -20 V)… read more here.
Keywords: voltage; back gate; nmos pmos; gate ... See more keywords
Suppression of Edge Effect Induced by Positive Gate Bias Stress in Low-Temperature Polycrystalline Silicon TFTs With Channel Width Extension Over Source/Drain Regions
Sign Up to like & getrecommendations! Published in 2020 at "IEEE Transactions on Electron Devices"
DOI: 10.1109/ted.2020.3033516
Abstract: This study demonstrated that the edge effect induced by positive gate bias stress (PBS) was effectively eliminated by applying channel width extensions over source/drain regions in low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs). After PBS,… read more here.
Keywords: extension; effect induced; channel width; edge effect ... See more keywords
High-Temperature Electrical and Thermal Aging Performance and Application Considerations for SiC Power DMOSFETs
Sign Up to like & getrecommendations! Published in 2017 at "IEEE Transactions on Power Electronics"
DOI: 10.1109/tpel.2016.2636743
Abstract: The temperature dependence and stability of three different commercially-available unpackaged SiC Dmosfets have been measured. On-state resistances increased to 6 or 7 times their room temperature values at 350 °C. Threshold voltages almost doubled after… read more here.
Keywords: gate bias; temperature; high temperature; power ... See more keywords
Model of the Effect of the Gate Bias on MOS Structures under Ionizing Radiation
Sign Up to like & getrecommendations! Published in 2020 at "Semiconductors"
DOI: 10.1134/s1063782620020025
Abstract: Abstract A new quantitative model of the effect of the gate bias on the threshold voltage of metal-oxide-semiconductor (MOS) structures under ionizing irradiation is developed based on the consideration of hole trapping from the entire… read more here.
Keywords: gate bias; model effect; gate; effect gate ... See more keywords
Gate-Bias-Induced Threshold Voltage Shifts in GaN FATFETs
Sign Up to like & getrecommendations! Published in 2023 at "ECS Journal of Solid State Science and Technology"
DOI: 10.1149/2162-8777/acd1b4
Abstract: The threshold voltage (V TH) stability in GaN fat field-effect transistors (FATFETs) with a large channel area of ∼6.2 × 104 μm2 was studied using drain current vs gate voltage (I D–V G) characteristics. Each… read more here.
Keywords: gan fatfets; bias induced; threshold voltage; voltage ... See more keywords
Improving the High-Temperature Gate Bias Instabilities by a Low Thermal Budget Gate-First Process in p-GaN Gate HEMTs
Sign Up to like & getrecommendations! Published in 2023 at "Micromachines"
DOI: 10.3390/mi14030576
Abstract: In this study, we report a low ohmic contact resistance process on a 650 V E-mode p-GaN gate HEMT structure. An amorphous silicon (a-Si) assisted layer was inserted in between the ohmic contact and GaN.… read more here.
Keywords: gate bias; gan gate; low thermal; gate ... See more keywords