Sidewall spacer layer engineering for improvement of analog/RF performance of nanoscale double-gate junctionless transistors
Sign Up to like & getrecommendations! Published in 2017 at "Microsystem Technologies"
DOI: 10.1007/s00542-016-3049-2
Abstract: We investigate the impact of sidewall spacers on the analog/RF performance of double gate junctionless transistors at channel length of 30 nm using extensive numerical device simulation. Furthermore, we report the performance of a common source… read more here.
Keywords: double gate; spacer; gain; analog performance ... See more keywords
Impact of different localized trap charge profiles on the short channel double gate junctionless nanowire transistor based inverter and Ring Oscillator circuit
Sign Up to like & getrecommendations! Published in 2019 at "AEU - International Journal of Electronics and Communications"
DOI: 10.1016/j.aeue.2019.06.014
Abstract: Abstract In this paper, the reliability issues due to localized charges on Double Gate Junctionless Nanowire Transistor (DG-JNT) based circuits are investigated. The localized/fixed charges come into existence at the interface of substrate and oxide… read more here.
Keywords: charge profiles; double gate; nanowire transistor; circuit ... See more keywords
Negative Capacitance Double-Gate Junctionless FETs: A Charge-Based Modeling Investigation of Swing, Overdrive and Short Channel Effect
Sign Up to like & getrecommendations! Published in 2020 at "IEEE Journal of the Electron Devices Society"
DOI: 10.1109/jeds.2020.3020976
Abstract: In this article, an analytical predictive model of the negative capacitance (NC) effect in symmetric long channel double-gate junctionless transistor is proposed based on a charge-based model. In particular, we have investigated the effect of… read more here.
Keywords: junctionless; negative capacitance; double gate; effect ... See more keywords
Upgrade of Drain Current Compact Model for Nanoscale Triple-Gate Junctionless Transistors to Continuous and Symmetric
Sign Up to like & getrecommendations! Published in 2019 at "IEEE Transactions on Electron Devices"
DOI: 10.1109/ted.2019.2937159
Abstract: In this brief, we upgrade our initial drain current compact model for triple-gate junctionless transistors (JLTs) to a continuous model satisfying the source/drain (S/D) symmetry. This is achieved by reformulating the key equations of our… read more here.
Keywords: compact model; triple gate; current compact; drain current ... See more keywords