Optimization of gate-stack in junctionless Si-nanotube FET for analog/RF applications
Sign Up to like & getrecommendations! Published in 2018 at "Materials Science in Semiconductor Processing"
DOI: 10.1016/j.mssp.2018.02.014
Abstract: Abstract In this work, gate-stack based junctionless Si-nanotube (JLSiNT) FET is studied to investigate the effect of high-K gate dielectric material in-conjunction with interfacial layer thickness (TI) and outer gate length (Lg) on analog/RF figures… read more here.
Keywords: gate; analog; junctionless nanotube; gate stack ... See more keywords
Roles of Oxygen Interstitial Defects in Atomic-Layer Deposited InGaZnO Thin Films with Controlling the Cationic Compositions and Gate-Stack Processes for the Devices with SubĪ¼m Channel Lengths.
Sign Up to like & getrecommendations! Published in 2022 at "ACS applied materials & interfaces"
DOI: 10.1021/acsami.2c07258
Abstract: Roles of oxygen interstitial defects located in the In-Ga-Zn-O (IGZO) thin films prepared by atomic layer deposition were investigated with controlling the cationic compositions and gate-stack process conditions. It was found from the spectroscopic ellipsometry… read more here.
Keywords: gate stack; oxygen interstitial; thin films; interstitial defects ... See more keywords
Enhanced gate stack stability in GaN transistors with gate dielectric of bilayer SiNx by low pressure chemical vapor deposition
Sign Up to like & getrecommendations! Published in 2018 at "Applied Physics Letters"
DOI: 10.1063/1.5042809
Abstract: We report enhanced gate stack stability in GaN metal insulator semiconductor high electron mobility transistors (MISHEMTs) by using a bilayer SiNx as the gate dielectric. To obtain the bilayer gate dielectric scheme, a thin Si-rich… read more here.
Keywords: gate dielectric; gate stack; bilayer sinx; bilayer ... See more keywords
Study on the charge trapping effect at the interface of ferroelectric/interlayer in the ferroelectric field effect transistor gate stack
Sign Up to like & getrecommendations! Published in 2023 at "Chinese Physics B"
DOI: 10.1088/1674-1056/acd524
Abstract: In this work, we study the charge trapping phenomenon that restricts the endurance of n-type ferroelectric field-effect transistors (FeFETs) with Metal/Ferroelectric/Interlayer/Si (MFIS)gate stack structure. In order to explore the physical mechanism of the endurance failure… read more here.
Keywords: gate stack; model; charge trapping; effect ... See more keywords
Modeling of Gate Stack Patterning for Advanced Technology Nodes: A Review
Sign Up to like & getrecommendations! Published in 2018 at "Micromachines"
DOI: 10.3390/mi9120631
Abstract: Semiconductor device dimensions have been decreasing steadily over the past several decades, generating the need to overcome fundamental limitations of both the materials they are made of and the fabrication techniques used to build them.… read more here.
Keywords: stack patterning; modeling gate; technology; patterning advanced ... See more keywords