High‐κ Dielectric (HfO2)/2D Semiconductor (HfSe2) Gate Stack for Low‐Power Steep‐Switching Computing Devices
Sign Up to like & getrecommendations! Published in 2024 at "Advanced Materials"
DOI: 10.1002/adma.202312747
Abstract: Herein, a high‐quality gate stack (native HfO2 formed on 2D HfSe2) fabricated via plasma oxidation is reported, realizing an atomically sharp interface with a suppressed interface trap density (Dit ≈ 5 × 1010 cm−2 eV−1).… read more here.
Keywords: steep switching; hfse2 gate; stack; gate stack ... See more keywords
Optimization of gate-stack in junctionless Si-nanotube FET for analog/RF applications
Sign Up to like & getrecommendations! Published in 2018 at "Materials Science in Semiconductor Processing"
DOI: 10.1016/j.mssp.2018.02.014
Abstract: Abstract In this work, gate-stack based junctionless Si-nanotube (JLSiNT) FET is studied to investigate the effect of high-K gate dielectric material in-conjunction with interfacial layer thickness (TI) and outer gate length (Lg) on analog/RF figures… read more here.
Keywords: gate; analog; junctionless nanotube; gate stack ... See more keywords
Ultra-High-k Ferroelectric BaTiO3 Perovskite in the Gate Stack for Two-Dimensional WSe2 p-Type High-Performance Transistors.
Sign Up to like & getrecommendations! Published in 2024 at "Nano letters"
DOI: 10.1021/acs.nanolett.4c02069
Abstract: The experimental demonstration of a p-type 2D WSe2 transistor with a ferroelectric perovskite BaTiO3 gate oxide is presented. The 30 nm thick BaTiO3 gate stack shows a robust ferroelectric hysteresis with a remanent polarization of… read more here.
Keywords: stack; batio3; perovskite gate; ultra high ... See more keywords
Roles of Oxygen Interstitial Defects in Atomic-Layer Deposited InGaZnO Thin Films with Controlling the Cationic Compositions and Gate-Stack Processes for the Devices with Subμm Channel Lengths.
Sign Up to like & getrecommendations! Published in 2022 at "ACS applied materials & interfaces"
DOI: 10.1021/acsami.2c07258
Abstract: Roles of oxygen interstitial defects located in the In-Ga-Zn-O (IGZO) thin films prepared by atomic layer deposition were investigated with controlling the cationic compositions and gate-stack process conditions. It was found from the spectroscopic ellipsometry… read more here.
Keywords: gate stack; oxygen interstitial; thin films; interstitial defects ... See more keywords
Interface States in Gate Stack of Carbon Nanotube Array Transistors.
Sign Up to like & getrecommendations! Published in 2024 at "ACS nano"
DOI: 10.1021/acsnano.4c03989
Abstract: A deep understanding of the interface states in metal-oxide-semiconductor (MOS) structures is the premise of improving the gate stack quality, which sets the foundation for building field-effect transistors (FETs) with high performance and high reliability.… read more here.
Keywords: carbon nanotube; gate stack; interface states;
Enhanced gate stack stability in GaN transistors with gate dielectric of bilayer SiNx by low pressure chemical vapor deposition
Sign Up to like & getrecommendations! Published in 2018 at "Applied Physics Letters"
DOI: 10.1063/1.5042809
Abstract: We report enhanced gate stack stability in GaN metal insulator semiconductor high electron mobility transistors (MISHEMTs) by using a bilayer SiNx as the gate dielectric. To obtain the bilayer gate dielectric scheme, a thin Si-rich… read more here.
Keywords: gate dielectric; gate stack; bilayer sinx; bilayer ... See more keywords
Study on the charge trapping effect at the interface of ferroelectric/interlayer in the ferroelectric field effect transistor gate stack
Sign Up to like & getrecommendations! Published in 2023 at "Chinese Physics B"
DOI: 10.1088/1674-1056/acd524
Abstract: In this work, we study the charge trapping phenomenon that restricts the endurance of n-type ferroelectric field-effect transistors (FeFETs) with Metal/Ferroelectric/Interlayer/Si (MFIS)gate stack structure. In order to explore the physical mechanism of the endurance failure… read more here.
Keywords: gate stack; model; charge trapping; effect ... See more keywords
Top-Gate Atomic-Layer-Deposited Oxide Semiconductor Transistors With Large Memory Window and Non-Ferroelectric HfO₂ Gate Stack
Sign Up to like & getrecommendations! Published in 2025 at "IEEE Electron Device Letters"
DOI: 10.1109/led.2025.3581599
Abstract: In this work, we demonstrate a top-gate indium-zinc oxide (IZO) transistor with non-ferroelectric HfO2 gate stack but exhibiting a counterclockwise hysteresis loop with large memory window (MW) of 2.7 V and long retention over 10… read more here.
Keywords: memory; non ferroelectric; gate; gate stack ... See more keywords
Atom-Scaled Hafnium Doping for Strengthening the Germanium Oxide Interfacial Layer of The Gate Stack of Germanium P-Type Metal-Oxide-Semiconductor Field Effect Transistor
Sign Up to like & getrecommendations! Published in 2024 at "ECS Journal of Solid State Science and Technology"
DOI: 10.1149/2162-8777/ad46f0
Abstract: We have developed a method that uses a half-cycle Hf precursor adsorption to subtly dope GeO2 IL of the Hf-based gate stack through in situ plasma-enhanced atomic layer deposition. This technique can effectively reduce GeO… read more here.
Keywords: layer; metal; atom scaled; gate stack ... See more keywords
Impact of Interface Trap Charges on Silicon Carbide (4H-SiC) Based Gate – Stack, Dual Metal, Surrounding Gate, FET (4H-SiC- GSDM-SGFET) for Analog and Noise Performance Analysis for 5G/LTE Applications
Sign Up to like & getrecommendations! Published in 2024 at "ECS Journal of Solid State Science and Technology"
DOI: 10.1149/2162-8777/ad6502
Abstract: This article examines the impact of various interface trap charges on silicon carbide-based gate – stack, dual metal, surrounding gate, FET (4H-SiC-GSDM-SGFET). It has been contrasted for performance with silicon carbide (4H-SiC)-based dual metal, surrounding… read more here.
Keywords: silicon carbide; dual metal; gate; trap charges ... See more keywords
Modeling of Gate Stack Patterning for Advanced Technology Nodes: A Review
Sign Up to like & getrecommendations! Published in 2018 at "Micromachines"
DOI: 10.3390/mi9120631
Abstract: Semiconductor device dimensions have been decreasing steadily over the past several decades, generating the need to overcome fundamental limitations of both the materials they are made of and the fabrication techniques used to build them.… read more here.
Keywords: stack patterning; modeling gate; technology; patterning advanced ... See more keywords