Area Optimized Synthesis of Compressor Trees on Xilinx FPGAs Using Generalized Parallel Counters
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DOI: 10.1109/access.2019.2941985
Abstract: Early compressor trees based on carry-save adders and single-column parallel counters show good performance in ASIC design, but do not adapt well to modern field-programmable gate arrays (FPGAs). Recently, compressor trees built from generalized parallel… read more here.
Keywords: compressor; area; compressor trees; generalized parallel ... See more keywords