Power Efficient Design of High-Performance Convolutional Neural Networks Hardware Accelerator on FPGA: A Case Study With GoogLeNet
Sign Up to like & getrecommendations! Published in 2021 at "IEEE Access"
DOI: 10.1109/access.2021.3126838
Abstract: Convolutional neural networks (CNNs) have dominated image recognition and object detection models in the last few years. They can achieve the highest accuracies with several applications such as automotive and biomedical applications. CNNs are usually… read more here.
Keywords: googlenet; power; convolutional neural; performance ... See more keywords
Effective Hardware Accelerator for 2D DCT/IDCT Using Improved Loeffler Architecture
Sign Up to like & getrecommendations! Published in 2022 at "IEEE Access"
DOI: 10.1109/access.2022.3146162
Abstract: This paper proposes an effective hardware accelerator for 2D $8\times 8$ discrete cosine transform (DCT) and inverse discrete cosine transform (IDCT) using an improved Loeffler architecture. The accelerator optimizes the data stream of the Loeffler… read more here.
Keywords: dct idct; architecture; dct; hardware accelerator ... See more keywords
Row-Wise Product-Based Sparse Matrix Multiplication Hardware Accelerator With Optimal Load Balancing
Sign Up to like & getrecommendations! Published in 2022 at "IEEE Access"
DOI: 10.1109/access.2022.3184116
Abstract: Matrix multiplication is a main computation kernel of emerging workloads, such as deep neural networks and graph analytics. These workloads often exhibit high sparsity in data, which means a large portion of the elements in… read more here.
Keywords: load balancing; matrix; product; hardware accelerator ... See more keywords
A Hardware Accelerator for Tracing Garbage Collection
Sign Up to like & getrecommendations! Published in 2019 at "IEEE Micro"
DOI: 10.1109/mm.2019.2910509
Abstract: Many workloads are written in garbage-collected languages and GC consumes a significant fraction of resources for these workloads. We propose to decrease this overhead by moving GC into a small hardware accelerator that is located… read more here.
Keywords: accelerator tracing; garbage; accelerator; hardware accelerator ... See more keywords
A Fast FPGA Hardware Accelerator for Remote Heart Rate Detection Based on RGB Vision
Sign Up to like & getrecommendations! Published in 2024 at "IEEE Transactions on Biomedical Circuits and Systems"
DOI: 10.1109/tbcas.2024.3354505
Abstract: A fast hardware accelerator is created by this work via field programmable gate array (FPGA) to estimate heart rate (HR) through the video recorded by a RGB camera based on the technology of remote photoplethysmography… read more here.
Keywords: heart; hardware accelerator; heart rate;
Huicore: A Generalized Hardware Accelerator for Complicated Functions
Sign Up to like & getrecommendations! Published in 2022 at "IEEE Transactions on Circuits and Systems I: Regular Papers"
DOI: 10.1109/tcsi.2022.3152799
Abstract: Emerging advanced System-on-Chip (SoC) designs contain more and more complicated functions to be accelerated. This presents a challenge to conventional design approaches which use different hardware architectures or separate hardware accelerators to implement the various… read more here.
Keywords: generalized hardware; hardware; huicore generalized; complicated functions ... See more keywords
Hardware Accelerator Design for Sparse DNN Inference and Training: A Tutorial
Sign Up to like & getrecommendations! Published in 2024 at "IEEE Transactions on Circuits and Systems II: Express Briefs"
DOI: 10.1109/tcsii.2023.3344681
Abstract: Deep neural networks (DNNs) are widely used in many fields, such as artificial intelligence generated content (AIGC) and robotics. To efficiently support these tasks, the model pruning technique is developed to compress the computational and… read more here.
Keywords: hardware accelerator; sparse dnn; sparse; design ... See more keywords
A Nonvolatile All-Spin Nonbinary Matrix Multiplier: An Efficient Hardware Accelerator for Machine Learning
Sign Up to like & getrecommendations! Published in 2022 at "IEEE Transactions on Electron Devices"
DOI: 10.1109/ted.2022.3214167
Abstract: We propose and analyze a compact and nonvolatile nanomagnetic (all-spin) nonbinary matrix multiplier performing the multiply-and-accumulate (MAC) operation using two magnetic tunnel junctions (MTJs)–one activated by strain to act as the multiplier and the other… read more here.
Keywords: matrix multiplier; nonbinary matrix; accelerator machine; machine learning ... See more keywords
VisionAGILE: A Versatile Domain-Specific Accelerator for Computer Vision Tasks
Sign Up to like & getrecommendations! Published in 2024 at "IEEE Transactions on Parallel and Distributed Systems"
DOI: 10.1109/tpds.2024.3466891
Abstract: The emergence of diverse machine learning (ML) models has led to groundbreaking revolutions in computer vision (CV). These ML models include convolutional neural networks (CNNs), graph neural networks (GNNs), and vision transformers (ViTs). However, existing… read more here.
Keywords: mml mml; hardware accelerator; mml; math ... See more keywords
A Variable-Size FFT Hardware Accelerator Based on Matrix Transposition
Sign Up to like & getrecommendations! Published in 2018 at "IEEE Transactions on Very Large Scale Integration (VLSI) Systems"
DOI: 10.1109/tvlsi.2018.2846688
Abstract: Fast Fourier transform (FFT) is the kernel and the most time-consuming algorithm in the domain of digital signal processing, and the FFT sizes of different applications are very different. Therefore, this paper proposes a variable-size… read more here.
Keywords: size; fft hardware; fft; hardware accelerator ... See more keywords
A Masked Hardware Accelerator for Feed-Forward Neural Networks With Fixed-Point Arithmetic
Sign Up to like & getrecommendations! Published in 2024 at "IEEE Transactions on Very Large Scale Integration (VLSI) Systems"
DOI: 10.1109/tvlsi.2023.3340553
Abstract: Neural network (NN) execution on resource-constrained edge devices is increasing. Commonly, hardware accelerators are introduced in small devices to support the execution of NNs. However, an attacker can often gain physical access to edge devices.… read more here.
Keywords: accelerator; masked hardware; fixed point; hardware accelerator ... See more keywords