Joint Motion Compensation and MC-Reused Spatial Error Concealment on Hardware Architecture Design
Sign Up to like & getrecommendations! Published in 2017 at "Journal of Signal Processing Systems"
DOI: 10.1007/s11265-016-1196-4
Abstract: Error concealment (EC) can recover visual quality, while transmission error occurs on video bitstream. Generally, EC is an extra function integrated into the video decoder and also consumes an additional hardware resource. It’s hardware architecture… read more here.
Keywords: hardware; hardware architecture; error concealment;
Modeling, hardware architecture, and performance analyses of an AEAD-based lightweight cipher
Sign Up to like & getrecommendations! Published in 2024 at "Journal of Real-Time Image Processing"
DOI: 10.1007/s11554-024-01416-w
Abstract: Ensuring data security and integrity is crucial for achieving the highest level of protection and performance in modern cyber-physical systems (CPS). Authenticated encryption with associated data (AEAD) is an efficient and secure way to encrypt… read more here.
Keywords: image; cipher; image encryption; performance ... See more keywords
Fast hardware architecture for fixed-point 2D Gaussian filter
Sign Up to like & getrecommendations! Published in 2019 at "AEU - International Journal of Electronics and Communications"
DOI: 10.1016/j.aeue.2019.03.020
Abstract: Abstract This study presents the hardware architecture for 16-bit, 5 × 5 fixed-point 2D Gaussian kernel. Two filters are proposed, one using generalized kernel and other using separable kernel. The quality analysis of both the… read more here.
Keywords: fixed point; performance; hardware architecture; filter ... See more keywords
Reconfigurable VLSI design of a changeable hybrid-radix FFT hardware architecture with 2D-FIFO storing structure for 3GPP LTE systems
Sign Up to like & getrecommendations! Published in 2018 at "ICT Express"
DOI: 10.1016/j.icte.2017.11.007
Abstract: Abstract This paper presents a reconfigurable Fast Fourier Transform (FFT) hardware architecture for 3GPP LTE systems. In the main FFT computing process, a novel processing kernel engine is proposed to support four configuration types of… read more here.
Keywords: fft; 3gpp lte; changeable hybrid; hardware architecture ... See more keywords
A generic FPGA-based hardware architecture for recursive least mean p-power extreme learning machine
Sign Up to like & getrecommendations! Published in 2021 at "Neurocomputing"
DOI: 10.1016/j.neucom.2021.05.069
Abstract: Abstract Recursive least mean p-power extreme learning machine (RLMP-ELM) is a newly proposed online machine learning algorithm and is able to provide a robust online prediction of the datasets with noises of different statistics. To… read more here.
Keywords: recursive least; least mean; hardware architecture; machine ... See more keywords
FPGA implementation of hardware architecture with AES encryptor using sub-pipelined S-box techniques for compact applications
Sign Up to like & getrecommendations! Published in 2020 at "Automatika"
DOI: 10.1080/00051144.2020.1816388
Abstract: Advanced Encryption Standard (AES) is a thriving cryptographic algorithm that can be utilized to guarantee security in electronic information. It remains to uphold to be resistive from most of the attacks. In this work, AES-128… read more here.
Keywords: implementation hardware; fpga implementation; encryption; box ... See more keywords
Hardware Architecture Proposal for TEDA Algorithm to Data Streaming Anomaly Detection
Sign Up to like & getrecommendations! Published in 2021 at "IEEE Access"
DOI: 10.1109/access.2021.3098004
Abstract: The amount of data in real-time, such as time series and streaming data, available today continues to grow. Being able to analyze this data the moment it arrives can bring an immense added value. However,… read more here.
Keywords: hardware architecture; architecture; teda algorithm; data streaming ... See more keywords
Implementation of Hardware Architecture for SVPWM with Arbitrary Parameters
Sign Up to like & getrecommendations! Published in 2022 at "IEEE Access"
DOI: 10.1109/access.2022.3160750
Abstract: A novel hardware digital architecture for the Space Vector PulseWidth Modulation technique is proposed. Its characteristics are the reduced demand for resources and the possibility to change in real-time the values of the carrier and… read more here.
Keywords: implementation hardware; hardware architecture; hardware; architecture svpwm ... See more keywords
Efficient Low-Latency Hardware Architecture for Module-Lattice-Based Digital Signature Standard
Sign Up to like & getrecommendations! Published in 2024 at "IEEE Access"
DOI: 10.1109/access.2024.3370470
Abstract: The rapid advancement of powerful quantum computers poses a significant security risk to current public-key cryptosystems, which heavily rely on the computational complexity of problems such as discrete logarithms and integer factorization. As a result,… read more here.
Keywords: latency; hardware; digital signature; hardware architecture ... See more keywords
One-dimensional filtering based two-bit transform and its efficient hardware architecture for fast motion estimation
Sign Up to like & getrecommendations! Published in 2017 at "IEEE Transactions on Consumer Electronics"
DOI: 10.1109/tce.2017.015085
Abstract: Video encoding is one of the most emerging application in many consumer electronics devices such as smartphones, tablets, cameras and camcorders in order to reduce required memory size for recording and utilized bandwidth for transmission… read more here.
Keywords: hardware; hardware architecture; motion estimation;
An FPGA-Based Autofocusing Hardware Architecture for Digital Holography
Sign Up to like & getrecommendations! Published in 2019 at "IEEE Transactions on Computational Imaging"
DOI: 10.1109/tci.2019.2892810
Abstract: A novel hardware architecture for the reconstruction of digital holograms with autofocusing is presented in this paper. The architecture is based on a novel autofocusing algorithm operating on a smaller local block located at the… read more here.
Keywords: fpga based; autofocusing hardware; hardware; hardware architecture ... See more keywords