FPGAN: An FPGA Accelerator for Graph Attention Networks With Software and Hardware Co-Optimization
Sign Up to like & getrecommendations! Published in 2020 at "IEEE Access"
DOI: 10.1109/access.2020.3023946
Abstract: The Graph Attention Networks (GATs) exhibit outstanding performance in multiple authoritative node classification benchmark tests (including transductive and inductive). The purpose of this research is to implement an FPGA-based accelerator called FPGAN for graph attention… read more here.
Keywords: graph attention; software hardware; hardware optimization; attention networks ... See more keywords
Pulley: An Algorithm/Hardware Co-Optimization for In-Memory Sorting
Sign Up to like & getrecommendations! Published in 2022 at "IEEE Computer Architecture Letters"
DOI: 10.1109/lca.2022.3208255
Abstract: Sorting is an important kernel that requires many passes on data, where each pass imposes significant data movement overhead. Processing in memory (PIM) can reduce this data movement overhead while providing high parallelism. The radix… read more here.
Keywords: optimization memory; algorithm hardware; pulley algorithm; hardware optimization ... See more keywords