Design of efficient binary multiplier architecture using hybrid compressor with FPGA implementation
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DOI: 10.1038/s41598-024-58482-0
Abstract: In signal processing applications, the multipliers are essential component of arithmetic functional units in many applications, like digital signal processors, image/video processing, Machine Learning, Cryptography and Arithmetic & Logical units (ALU). In recent years, Profuse… read more here.
Keywords: vedic multiplier; hybrid compressor; using hybrid; compressor ... See more keywords