Hardware Implementation of a Fixed-Point Decoder for Low-Density Lattice Codes
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DOI: 10.1007/s11265-021-01735-2
Abstract: This paper describes a field-programmable gate array (FPGA) implementation of a fixed-point low-density lattice code (LDLC) decoder where the Gaussian mixture messages that are exchanged during the iterative decoding process are approximated to a single… read more here.
Keywords: implementation fixed; decoder; fixed point; low density ... See more keywords