On-Chip Characterization of Ultra-Low Voltage Standard Cell Library Considering Input Slew and Output Capacitance
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DOI: 10.1109/ted.2023.3319598
Abstract: The propagation delay of a logic gate in a standard cell library (SCL) primarily depends on the input transition time (slew) and output load capacitance. In this article, we proposed an area-efficient test structure, which… read more here.
Keywords: standard cell; logic; slew output; input slew ... See more keywords