An ASIC Architecture With Inter-Chip Networking for Individual Control of Adaptive-Metamaterial Cells
Sign Up to like & getrecommendations! Published in 2022 at "IEEE Access"
DOI: 10.1109/access.2022.3194601
Abstract: In this paper, the architecture of an application-specific integrated circuit for adaptive metasurfaces is presented. The architecture allows scalable networking over large metasurfaces and reconfiguration of each unit-cell with unique complex impedance settings, for adjusting… read more here.
Keywords: architecture inter; asic architecture; chip networking; architecture ... See more keywords
Methods for Estimating the Convergence of Inter-Chip Min-Entropy of SRAM PUFs
Sign Up to like & getrecommendations! Published in 2018 at "IEEE Transactions on Circuits and Systems I: Regular Papers"
DOI: 10.1109/tcsi.2017.2733582
Abstract: For cryptographic applications based on physical unclonable functions (PUFs), it is very important to estimate the entropy of PUF responses accurately. The upper bound of the entropy estimated by compression algorithms, such as context-tree weighting,… read more here.
Keywords: inter chip; convergence inter; min entropy; entropy ... See more keywords
Via-Avoidance-Oriented Interposer Routing for Layer Minimization in 2.5-D IC Designs
Sign Up to like & getrecommendations! Published in 2021 at "IEEE Transactions on Very Large Scale Integration (VLSI) Systems"
DOI: 10.1109/tvlsi.2021.3113918
Abstract: It is well known that interposer-based 2.5-D integrated circuit (IC) designs have become one of the most promising solutions for providing yield improvement, enhancing system performance, decreasing power consumption, and supporting heterogeneous integration. In this… read more here.
Keywords: layer; sub nets; inter chip; silicon ... See more keywords