A 27-Gb/s Time-Interleaved Duobinary Transmitter Achieving 1.44-mW/Gb/s FOM in 65-nm CMOS
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DOI: 10.1109/lmwc.2017.2735548
Abstract: A time-interleaved duobinary transmitter featuring four-way data retiming and a simplified latch + D flip-flop topology to improve the power efficiency and opening of the data eye is reported. A modified bridged shunt-peaking load using… read more here.
Keywords: time interleaved; transmitter achieving; duobinary transmitter; interleaved duobinary ... See more keywords