Design Flow for Active Interposer-Based 2.5-D ICs and Study of RISC-V Architecture With Secure NoC
Sign Up to like & getrecommendations! Published in 2020 at "IEEE Transactions on Components, Packaging and Manufacturing Technology"
DOI: 10.1109/tcpmt.2020.3033136
Abstract: Interposer-based 2.5-D integrated circuits (ICs) enable the chip-level reuse of hard intellectual properties (IPs), also known as chiplets. Such system-level integration shortens the design cycle considerably for large-scale and heterogeneous chips. Besides traditional interposers, which… read more here.
Keywords: interposer; flow active; active interposer; design ... See more keywords
Co-Integrated PIN-PMN-PT 2-D Array and Transceiver Electronics by Direct Assembly Using a 3-D Printed Interposer Grid Frame
Sign Up to like & getrecommendations! Published in 2020 at "IEEE Transactions on Ultrasonics, Ferroelectrics, and Frequency Control"
DOI: 10.1109/tuffc.2019.2944668
Abstract: Tiled modular 2-D ultrasound arrays have the potential for realizing large apertures for novel diagnostic applications. This work presents an architecture for fabrication of tileable 2-D array modules implemented using 1–3 composites of high-bandwidth (BW)… read more here.
Keywords: tex math; array; inline formula; interposer ... See more keywords
Architecture, Chip, and Package Codesign Flow for Interposer-Based 2.5-D Chiplet Integration Enabling Heterogeneous IP Reuse
Sign Up to like & getrecommendations! Published in 2020 at "IEEE Transactions on Very Large Scale Integration (VLSI) Systems"
DOI: 10.1109/tvlsi.2020.3015494
Abstract: A new trend in system-on-chip (SoC) design is chiplet-based IP reuse using 2.5-D integration. Complete electronic systems can be created through the integration of chiplets on an interposer, rather than through a monolithic flow. This… read more here.
Keywords: interposer; integration; chip; package ... See more keywords
Via-Avoidance-Oriented Interposer Routing for Layer Minimization in 2.5-D IC Designs
Sign Up to like & getrecommendations! Published in 2021 at "IEEE Transactions on Very Large Scale Integration (VLSI) Systems"
DOI: 10.1109/tvlsi.2021.3113918
Abstract: It is well known that interposer-based 2.5-D integrated circuit (IC) designs have become one of the most promising solutions for providing yield improvement, enhancing system performance, decreasing power consumption, and supporting heterogeneous integration. In this… read more here.
Keywords: layer; sub nets; inter chip; silicon ... See more keywords
Reliability Assessment of Thermocompressed Epoxy Molding Compound through Glass via Interposer Architecture by the Submodeling Simulation Approach
Sign Up to like & getrecommendations! Published in 2022 at "Materials"
DOI: 10.3390/ma15207357
Abstract: In glass interposer architecture and its assembly process, the mechanical responses of interposer structure under thermocompression process-induced thermal loading and generated shrinkage of molding material are regarded as a major reliability issue. Thousands of metal-filled… read more here.
Keywords: interposer; simulation; glass; approach ... See more keywords