Modeling of the degradation of CMOS inverters under pulsed stress conditions from ‘on-the-fly’ measurements
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DOI: 10.1016/j.sse.2021.108094
Abstract: Abstract In this work, an ‘on-the-fly’ measurement technique for the monitoring of CMOS inverters performance degradation is presented. This technique allows the characterization of the circuit degradation simultaneously with the applications of the stress. In… read more here.
Keywords: voltage; modeling degradation; inverters pulsed; degradation cmos ... See more keywords