FPGA-based burst-error performance analysis and optimization of regular and irregular SD-LDPC codes for 50G-PON and beyond.
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DOI: 10.1364/oe.477546
Abstract: We evaluate the burst-error performance of the regular low-density parity-check (LDPC) code and the irregular LDPC code that has been considered for ITU-T's 50G-PON standard via experimental measurements in FPGA. By using intra codeword interleaving… read more here.
Keywords: ldpc; irregular ldpc; error performance; 50g pon ... See more keywords