Optimization of gate-stack in junctionless Si-nanotube FET for analog/RF applications
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DOI: 10.1016/j.mssp.2018.02.014
Abstract: Abstract In this work, gate-stack based junctionless Si-nanotube (JLSiNT) FET is studied to investigate the effect of high-K gate dielectric material in-conjunction with interfacial layer thickness (TI) and outer gate length (Lg) on analog/RF figures… read more here.
Keywords: gate; analog; junctionless nanotube; gate stack ... See more keywords