Pinning Page Structure Entries to Last-Level Cache for Fast Address Translation
Sign Up to like & getrecommendations! Published in 2022 at "IEEE Access"
DOI: 10.1109/access.2022.3217484
Abstract: As the memory footprint of emerging applications continues to increase, the address translation becomes a critical performance bottleneck owing to frequent misses on the Translation Lookaside Buffer (TLB). In addition, the TLB miss penalty becomes… read more here.
Keywords: page; last level; tlb; page structure ... See more keywords
An Eight-Core RISC-V Processor With Compute Near Last Level Cache in Intel 4 CMOS
Sign Up to like & getrecommendations! Published in 2023 at "IEEE Journal of Solid-State Circuits"
DOI: 10.1109/jssc.2022.3228765
Abstract: An eight-core 64-b processor extends RISC-V to perform multiply–accumulate (MAC) within the shared last level cache (LLC). Instead of moving data from the LLC to the core, compute near last level cache (CNC) adds MAC… read more here.
Keywords: level cache; inline formula; last level; tex math ... See more keywords
Last-Level Cache Insertion and Promotion Policy in the Presence of Aggressive Prefetching
Sign Up to like & getrecommendations! Published in 2023 at "IEEE Computer Architecture Letters"
DOI: 10.1109/lca.2023.3242178
Abstract: The last-level cache (LLC) is the last chance for memory accesses from the processor to avoid the costly latency of going to main memory. LLC management has been the topic of intense research focusing on… read more here.
Keywords: presence aggressive; replacement; level cache; policy ... See more keywords
BlendCache: An Energy and Area Efficient Racetrack Last-Level-Cache Architecture
Sign Up to like & getrecommendations! Published in 2022 at "IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"
DOI: 10.1109/tcad.2022.3161198
Abstract: Racetrack memory (RTM) is a promising nonvolatile memory that provides multibit storage cells achieving a higher area and leakage energy efficiency compared to contemporary volatile and nonvolatile memories. These features make RTM a potential candidate… read more here.
Keywords: racetrack; level cache; area; energy ... See more keywords
Taming Process Variations in CNFET for Efficient Last-Level Cache Design
Sign Up to like & getrecommendations! Published in 2022 at "IEEE Transactions on Very Large Scale Integration (VLSI) Systems"
DOI: 10.1109/tvlsi.2021.3135502
Abstract: Carbon nanotube field-effect transistors (CNFETs) emerge as a promising alternative to CMOS transistors for the much higher speed and energy efficiency, which makes the technology particularly suitable for building the energy-hungry last-level cache (LLC). However,… read more here.
Keywords: last level; cache; level cache; process variations ... See more keywords