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Published in 2021 at "Analog Integrated Circuits and Signal Processing"
DOI: 10.1007/s10470-021-01863-6
Abstract: The next generation of non-volatile memory elements have been attracting significant attention for future emerging memory applications in recent years. Several technologies have been developed to occupy a new field in storage-class memory and even…
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Keywords:
volatile latch;
non volatile;
memory;
topology ... See more keywords
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Published in 2018 at "Biophysical Journal"
DOI: 10.1016/j.bpj.2017.11.1798
Abstract: Smooth muscle has a unique property, called the latch-state, during which force is maintained for long periods of time at low energy consumption and low myosin activation (phosphorylation) levels. This property has been observed at…
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Keywords:
latch state;
myosin;
muscle;
level ... See more keywords
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Published in 2025 at "Scientific Reports"
DOI: 10.1038/s41598-025-02619-2
Abstract: Today, the implementation of computer systems and digital circuits is done using CMOS (complementary metal oxide semiconductor) technology, but problems such as high-power consumption and physical limitations of CMOS have led researchers to use the…
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Keywords:
technology;
consumption;
quantum dot;
latch ... See more keywords
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Published in 2018 at "Journal of Semiconductors"
DOI: 10.1088/1674-4926/39/5/055003
Abstract: This paper proposes a latch that can mitigate SEUs via an error detection circuit. The error detection circuit is hardened by a C-element and a stacked PMOS. In the hold state, a particle strikes the…
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Keywords:
error detection;
error;
latch;
detection circuit ... See more keywords
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Published in 2020 at "IEEE Access"
DOI: 10.1109/access.2020.3008225
Abstract: Multiple-node upsets (MNUs) caused by charge sharing effects are dramatically increasing in advanced nanoscale digital latches. Consequently, the robust latches against MNU cases are increasingly important. Although some existing robust latches are designed to recover…
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Keywords:
node upset;
latch;
multiple node;
mnu cases ... See more keywords
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Published in 2021 at "IEEE Access"
DOI: 10.1109/access.2021.3104335
Abstract: Due to semiconductor technology scaling, integrated circuits have become more sensitive to soft errors. To effectively tolerate multi-node-upsets caused by soft errors and reduce the power dissipation and delay of a latch, this paper proposes…
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Keywords:
triple node;
power;
self recoverable;
delay ... See more keywords
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Published in 2019 at "IEEE Robotics and Automation Letters"
DOI: 10.1109/lra.2019.2897006
Abstract: Single-incision laparoscopic surgery (SILS) has emerged as a procedure to further improve cosmetic profits and reduce the postoperative pain of multiport laparoscopic surgery. However, SILS is a difficult operation due to the limited workspace or…
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Keywords:
flexible joint;
force;
mechanism;
shape locking ... See more keywords
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Published in 2025 at "IEEE Transactions on Aerospace and Electronic Systems"
DOI: 10.1109/taes.2025.3581546
Abstract: With the continuous shrinking of nanoscale complementary metal-oxide-semiconductor (CMOS) technology, the critical charge of circuit nodes has significantly decreased, rendering the nodes highly susceptible to soft errors. In this article, a high-performance single-node-upset recovery memory…
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Keywords:
node upset;
latch;
quad hsrm;
recovery ... See more keywords
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Published in 2024 at "IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"
DOI: 10.1109/tcad.2024.3360314
Abstract: Flip-flops (FFs) are the most commonly used sequential elements in synchronous circuits, but their timing requirements limit the operating frequency. Borrowing time with a latch-based approach can increase operating frequency, but traditional back-end optimization tools…
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Keywords:
state art;
art retiming;
mix latch;
latch ... See more keywords
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1
Published in 2019 at "IEEE Transactions on Electron Devices"
DOI: 10.1109/ted.2019.2898317
Abstract: A new optimization design of an active guard ring has been proposed to improve latch-up immunity of CMOS integrated circuits and been successfully verified in a 0.18- $\mu \text{m}$ 1.8-/3.3-V CMOS technology. Codesigned with the…
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Keywords:
tex math;
latch immunity;
inline formula;
latch ... See more keywords
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Published in 2020 at "IEEE Transactions on Emerging Topics in Computing"
DOI: 10.1109/tetc.2017.2776285
Abstract: As the process feature size continues to scale down, the susceptibility of logic circuits to radiation induced error has increased. This trend has led to the increase in sensitivity of circuits to multi-node upsets. Previously,…
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Keywords:
dnu tolerant;
tolerant latch;
triple node;
node upsets ... See more keywords