Articles with "latch" as a keyword



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An optimization of a non-volatile latch using memristors for sequential circuit applications

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Published in 2021 at "Analog Integrated Circuits and Signal Processing"

DOI: 10.1007/s10470-021-01863-6

Abstract: The next generation of non-volatile memory elements have been attracting significant attention for future emerging memory applications in recent years. Several technologies have been developed to occupy a new field in storage-class memory and even… read more here.

Keywords: volatile latch; non volatile; memory; topology ... See more keywords
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Can We Reproduce the Latch-State in Vitro at the Molecular Level?

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Published in 2018 at "Biophysical Journal"

DOI: 10.1016/j.bpj.2017.11.1798

Abstract: Smooth muscle has a unique property, called the latch-state, during which force is maintained for long periods of time at low energy consumption and low myosin activation (phosphorylation) levels. This property has been observed at… read more here.

Keywords: latch state; myosin; muscle; level ... See more keywords
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An advanced SEU tolerant latch based on error detection

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Published in 2018 at "Journal of Semiconductors"

DOI: 10.1088/1674-4926/39/5/055003

Abstract: This paper proposes a latch that can mitigate SEUs via an error detection circuit. The error detection circuit is hardened by a C-element and a stacked PMOS. In the hold state, a particle strikes the… read more here.

Keywords: error detection; error; latch; detection circuit ... See more keywords
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Design of Robust Latch for Multiple-Node Upset (MNU) Mitigation in Nanoscale CMOS Technology

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Published in 2020 at "IEEE Access"

DOI: 10.1109/access.2020.3008225

Abstract: Multiple-node upsets (MNUs) caused by charge sharing effects are dramatically increasing in advanced nanoscale digital latches. Consequently, the robust latches against MNU cases are increasingly important. Although some existing robust latches are designed to recover… read more here.

Keywords: node upset; latch; multiple node; mnu cases ... See more keywords
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Design of a Highly Robust Triple-Node-Upset Self-Recoverable Latch

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Published in 2021 at "IEEE Access"

DOI: 10.1109/access.2021.3104335

Abstract: Due to semiconductor technology scaling, integrated circuits have become more sensitive to soft errors. To effectively tolerate multi-node-upsets caused by soft errors and reduce the power dissipation and delay of a latch, this paper proposes… read more here.

Keywords: triple node; power; self recoverable; delay ... See more keywords
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Shape-Locking Mechanism of Flexible Joint Using Mechanical Latch With Electromagnetic Force

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Published in 2019 at "IEEE Robotics and Automation Letters"

DOI: 10.1109/lra.2019.2897006

Abstract: Single-incision laparoscopic surgery (SILS) has emerged as a procedure to further improve cosmetic profits and reduce the postoperative pain of multiport laparoscopic surgery. However, SILS is a difficult operation due to the limited workspace or… read more here.

Keywords: flexible joint; force; mechanism; shape locking ... See more keywords
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Optimization Design on Active Guard Ring to Improve Latch-Up Immunity of CMOS Integrated Circuits

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Published in 2019 at "IEEE Transactions on Electron Devices"

DOI: 10.1109/ted.2019.2898317

Abstract: A new optimization design of an active guard ring has been proposed to improve latch-up immunity of CMOS integrated circuits and been successfully verified in a 0.18- $\mu \text{m}$ 1.8-/3.3-V CMOS technology. Codesigned with the… read more here.

Keywords: tex math; latch immunity; inline formula; latch ... See more keywords
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Radiation Hardened Latch Designs for Double and Triple Node Upsets

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Published in 2020 at "IEEE Transactions on Emerging Topics in Computing"

DOI: 10.1109/tetc.2017.2776285

Abstract: As the process feature size continues to scale down, the susceptibility of logic circuits to radiation induced error has increased. This trend has led to the increase in sensitivity of circuits to multi-node upsets. Previously,… read more here.

Keywords: dnu tolerant; tolerant latch; triple node; node upsets ... See more keywords
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Novel Quadruple-Node-Upset-Tolerant Latch Designs With Optimized Overhead for Reliable Computing in Harsh Radiation Environments

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Published in 2022 at "IEEE Transactions on Emerging Topics in Computing"

DOI: 10.1109/tetc.2020.3025584

Abstract: With the rapid advancement of CMOS technologies, nano-scale CMOS latches have become increasingly sensitive to multiple-node upset (MNU) errors caused by radiations. First, this paper proposes a novel latch design, namely QNUTL that can completely… read more here.

Keywords: tolerant latch; quadruple node; node upsets; node upset ... See more keywords
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Design of an Energy-Efficient Radiation-Hardened Non-Volatile Magnetic Latch

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Published in 2021 at "IEEE Transactions on Magnetics"

DOI: 10.1109/tmag.2020.3033229

Abstract: By scaling down the technology node to the deep nanoscale, the vulnerability of digital circuits to radiation and the intensive increase of leakage power have become of concern. Accordingly, designing radiation-hardened (rad-hard) memory elements based… read more here.

Keywords: radiation hardened; non volatile; energy efficient; rad hard ... See more keywords
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Ultra-Efficient and Robust Auto-Nonvolatile Schmitt Trigger-Based Latch Design Using Ferroelectric CNTFET Technology

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Published in 2022 at "IEEE Transactions on Ultrasonics, Ferroelectrics, and Frequency Control"

DOI: 10.1109/tuffc.2022.3158822

Abstract: In designing ultra-efficient noise immune nanoscale circuits and systems, Schmitt triggers (STs) are vital components influencing total functionality. This article proposes an ultracompact ST using ferroelectric carbon nanotube field-effect transistors (Fe-CNTFETs) and a robust ST… read more here.

Keywords: cntfet technology; auto; ultra efficient; design ... See more keywords