Simulation Study of Vertically Stacked Lateral Si Nanowires Transistors for 5-nm CMOS Applications
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DOI: 10.1109/jeds.2017.2752465
Abstract: In this paper, we present a simulation study of vertically stacked lateral nanowires transistors (NWTs), which may have applications at 5-nm CMOS technology. Our simulation approach is based on a collection of simulation techniques to… read more here.
Keywords: lateral nanowires; study vertically; simulation study; vertically stacked ... See more keywords