Model-Based Design of Flexible and Efficient LDPC Decoders on FPGA Devices
Sign Up to like & getrecommendations! Published in 2020 at "Journal of Signal Processing Systems"
DOI: 10.1007/s11265-020-01519-0
Abstract: Advances in digital communication advocate for the use of hardware LDPC decoders in applications requiring reliable and fast information transfer. Hand-coded RTL architectures provide the highest performances but slower the path to IP design. By… read more here.
Keywords: based design; ldpc; ldpc decoders; model based ... See more keywords
Fast-Converging and Low-Power LDPC Decoding: Algorithm, Architecture, and VLSI Implementation
Sign Up to like & getrecommendations! Published in 2021 at "Journal of Signal Processing Systems"
DOI: 10.1007/s11265-021-01680-0
Abstract: Low-latency and energy-efficient multi-Gbps LDPC decoding requires fast-converging iterative schedules. Hardware decoder architectures based on such schedules can achieve high throughput at low clock speeds, resulting in reduced power consumption and relaxed timing closure requirements… read more here.
Keywords: fast converging; power; ldpc; ldpc decoding ... See more keywords
A Flexible FPGA-Based Quasi-Cyclic LDPC Decoder
Sign Up to like & getrecommendations! Published in 2017 at "IEEE Access"
DOI: 10.1109/access.2017.2678103
Abstract: Low-density parity check (LDPC) error correction decoders have become popular in diverse communications systems, owing to their strong error correction performance and their suitability to parallel hardware implementation. A great deal of research effort has… read more here.
Keywords: ldpc decoder; ldpc; fpga based; quasi cyclic ... See more keywords
Algebra-Assisted Construction of Quasi-Cyclic LDPC Codes for 5G New Radio
Sign Up to like & getrecommendations! Published in 2018 at "IEEE Access"
DOI: 10.1109/access.2018.2868963
Abstract: Quasi-cyclic LDPC (QC-LDPC) codes have been accepted as the standard codes of 5G enhanced mobile broadband data channel. These standard codes are designed to support multiple lifting sizes and possess rate-compatible property, which can help… read more here.
Keywords: algebra assisted; cyclic ldpc; ldpc; ldpc codes ... See more keywords
Optimization of Non-Binary LDPC Coded Massive MIMO Systems With Partial Mapping and REP Detection
Sign Up to like & getrecommendations! Published in 2022 at "IEEE Access"
DOI: 10.1109/access.2022.3147273
Abstract: In this work, a non-binary low density parity check (LDPC) coded high dimensional multiple input multiple output (MIMO) scheme with partial mapping for high order modulation is proposed. For the proposed scheme, when $M$ -ary… read more here.
Keywords: ldpc; tex math; partial mapping; inline formula ... See more keywords
Construction of short-block nonbinary LDPC codes based on cyclic codes
Sign Up to like & getrecommendations! Published in 2017 at "China Communications"
DOI: 10.1109/cc.2017.8014342
Abstract: In this paper, we focus on short-block nonbinary LDPC (NB-LDPC) codes based on cyclic codes. Based on Tanner graphs' isomorphism, we present an efficient search algorithm for finding non-isomorphic binary cyclic LDPC codes. Notice that… read more here.
Keywords: block nonbinary; ldpc; nonbinary ldpc; short block ... See more keywords
Adaptive Artificial Neural Network-Coupled LDPC ECC as Universal Solution for 3-D and 2-D, Charge-Trap and Floating-Gate NAND Flash Memories
Sign Up to like & getrecommendations! Published in 2019 at "IEEE Journal of Solid-State Circuits"
DOI: 10.1109/jssc.2018.2884949
Abstract: Adaptive artificial neural network (ANN)-coupled low-density parity-check (LDPC) error-correcting code (ECC) (ANN-LDPC ECC) is proposed to increase acceptable errors for various NAND flash memories. The proposed ANN-LDPC ECC can be the universal solutions for 3-D… read more here.
Keywords: ldpc; ann ldpc; charge trap; floating gate ... See more keywords
Integrated Design of JSCC Scheme Based on Double Protograph LDPC Codes System
Sign Up to like & getrecommendations! Published in 2019 at "IEEE Communications Letters"
DOI: 10.1109/lcomm.2018.2890243
Abstract: In this letter, an integrated design of joint source-channel coding scheme based on the double protograph low-density parity-check (DP-LDPC) codes is proposed. As degree-2 variable nodes (VNs) structure plays an important role in the performance… read more here.
Keywords: ldpc; ldpc codes; integrated design; scheme based ... See more keywords
Improving Asymptotic Properties of Loop Construction of SC-LDPC Chains Over the BEC
Sign Up to like & getrecommendations! Published in 2022 at "IEEE Communications Letters"
DOI: 10.1109/lcomm.2021.3138613
Abstract: Single SC-LDPC chains are known to provide protographs of SC-LDPC codes. These chains can be connected together and create new constructions which provide multi-dimensional (MD) SC-LDPC codes. The loop is one of the most important… read more here.
Keywords: ldpc chains; ldpc; asymptotic properties; improving asymptotic ... See more keywords
Lower Bounds of Regular QC-LDPC Codes and SES Generation Algorithm
Sign Up to like & getrecommendations! Published in 2022 at "IEEE Communications Letters"
DOI: 10.1109/lcomm.2022.3154799
Abstract: In this letter we propose a new approach to generation of regular QC-LDPC codes with girth up to 12. The aim of the proposed smart exhaustive search (SES) algorithm is to construct codes with the… read more here.
Keywords: lower bounds; ldpc codes; ldpc; regular ldpc ... See more keywords
A Novel Base Graph Based Static Scheduling Scheme for Layered Decoding of 5G LDPC Codes
Sign Up to like & getrecommendations! Published in 2022 at "IEEE Communications Letters"
DOI: 10.1109/lcomm.2022.3171658
Abstract: Quasi-cyclic low-density parity-check (QC-LDPC) codes have been selected as the channel coding scheme for 5G new radio (NR) data channel. In this letter, a novel base graph based static scheduling (BGSS) method is proposed for… read more here.
Keywords: novel base; ldpc codes; ldpc; graph based ... See more keywords