Articles with "ldpc" as a keyword



Model-Based Design of Flexible and Efficient LDPC Decoders on FPGA Devices

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Published in 2020 at "Journal of Signal Processing Systems"

DOI: 10.1007/s11265-020-01519-0

Abstract: Advances in digital communication advocate for the use of hardware LDPC decoders in applications requiring reliable and fast information transfer. Hand-coded RTL architectures provide the highest performances but slower the path to IP design. By… read more here.

Keywords: based design; ldpc; ldpc decoders; model based ... See more keywords

Fast-Converging and Low-Power LDPC Decoding: Algorithm, Architecture, and VLSI Implementation

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Published in 2021 at "Journal of Signal Processing Systems"

DOI: 10.1007/s11265-021-01680-0

Abstract: Low-latency and energy-efficient multi-Gbps LDPC decoding requires fast-converging iterative schedules. Hardware decoder architectures based on such schedules can achieve high throughput at low clock speeds, resulting in reduced power consumption and relaxed timing closure requirements… read more here.

Keywords: fast converging; power; ldpc; ldpc decoding ... See more keywords

Dual-Discriminator Conditional Generative Adversarial Network-based LDPC-Coded OFDM Free-Space OCS for Improving BER Analysis

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Published in 2024 at "IETE Journal of Research"

DOI: 10.1080/03772063.2024.2434590

Abstract: This paper proposes a Dual-Discriminator Conditional Generative Adversarial Network-based LDPC-Coded OFDM Free-Space OCS for Improving BER Analysis (LDPC-OFDM-FSO-DDcGAN). The proposed LDPC-OFDM-FSO-DDcGAN method containsthe transmitter model, the channel model and the receiver model. The binary data… read more here.

Keywords: ldpc; fso ddcgan; model; discriminator conditional ... See more keywords

A Flexible FPGA-Based Quasi-Cyclic LDPC Decoder

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Published in 2017 at "IEEE Access"

DOI: 10.1109/access.2017.2678103

Abstract: Low-density parity check (LDPC) error correction decoders have become popular in diverse communications systems, owing to their strong error correction performance and their suitability to parallel hardware implementation. A great deal of research effort has… read more here.

Keywords: ldpc decoder; ldpc; fpga based; quasi cyclic ... See more keywords
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Algebra-Assisted Construction of Quasi-Cyclic LDPC Codes for 5G New Radio

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Published in 2018 at "IEEE Access"

DOI: 10.1109/access.2018.2868963

Abstract: Quasi-cyclic LDPC (QC-LDPC) codes have been accepted as the standard codes of 5G enhanced mobile broadband data channel. These standard codes are designed to support multiple lifting sizes and possess rate-compatible property, which can help… read more here.

Keywords: algebra assisted; cyclic ldpc; ldpc; ldpc codes ... See more keywords

Optimization of Non-Binary LDPC Coded Massive MIMO Systems With Partial Mapping and REP Detection

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Published in 2022 at "IEEE Access"

DOI: 10.1109/access.2022.3147273

Abstract: In this work, a non-binary low density parity check (LDPC) coded high dimensional multiple input multiple output (MIMO) scheme with partial mapping for high order modulation is proposed. For the proposed scheme, when $M$ -ary… read more here.

Keywords: ldpc; tex math; partial mapping; inline formula ... See more keywords

Tanner (3, 23)-Regular QC-LDPC Codes: Cycle Structure and Girth Distribution

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Published in 2024 at "IEEE Access"

DOI: 10.1109/access.2024.3355926

Abstract: This paper studies a class of quasi-cyclic LDPC (QC-LDPC) codes, i.e., Tanner (3, 23)-regular QC-LDPC codes of code length $23p$ with $p$ being a prime and $p \equiv 1 (\mathrm {mod} 69)$ . We first… read more here.

Keywords: ldpc; ldpc codes; inline formula; tex math ... See more keywords

Next-Gen Decoding: Non-Binary LDPC Algorithms for Emerging Power Line and Visible Light Communications

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Published in 2025 at "IEEE Access"

DOI: 10.1109/access.2025.3578151

Abstract: Non-Binary Low-Density Parity-Check (LDPC) codes have gained significant attention due to their remarkable error correction capabilities in various communication systems. Decoding algorithms play a pivotal role in realizing the potential of non-binary LDPC codes. This… read more here.

Keywords: ldpc; ldpc decoding; non binary; communication ... See more keywords

Construction of short-block nonbinary LDPC codes based on cyclic codes

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Published in 2017 at "China Communications"

DOI: 10.1109/cc.2017.8014342

Abstract: In this paper, we focus on short-block nonbinary LDPC (NB-LDPC) codes based on cyclic codes. Based on Tanner graphs' isomorphism, we present an efficient search algorithm for finding non-isomorphic binary cyclic LDPC codes. Notice that… read more here.

Keywords: block nonbinary; ldpc; nonbinary ldpc; short block ... See more keywords

Adaptive Artificial Neural Network-Coupled LDPC ECC as Universal Solution for 3-D and 2-D, Charge-Trap and Floating-Gate NAND Flash Memories

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Published in 2019 at "IEEE Journal of Solid-State Circuits"

DOI: 10.1109/jssc.2018.2884949

Abstract: Adaptive artificial neural network (ANN)-coupled low-density parity-check (LDPC) error-correcting code (ECC) (ANN-LDPC ECC) is proposed to increase acceptable errors for various NAND flash memories. The proposed ANN-LDPC ECC can be the universal solutions for 3-D… read more here.

Keywords: ldpc; ann ldpc; charge trap; floating gate ... See more keywords

Integrated Design of JSCC Scheme Based on Double Protograph LDPC Codes System

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Published in 2019 at "IEEE Communications Letters"

DOI: 10.1109/lcomm.2018.2890243

Abstract: In this letter, an integrated design of joint source-channel coding scheme based on the double protograph low-density parity-check (DP-LDPC) codes is proposed. As degree-2 variable nodes (VNs) structure plays an important role in the performance… read more here.

Keywords: ldpc; ldpc codes; integrated design; scheme based ... See more keywords