A Flexible FPGA-Based Quasi-Cyclic LDPC Decoder
Sign Up to like & getrecommendations! Published in 2017 at "IEEE Access"
DOI: 10.1109/access.2017.2678103
Abstract: Low-density parity check (LDPC) error correction decoders have become popular in diverse communications systems, owing to their strong error correction performance and their suitability to parallel hardware implementation. A great deal of research effort has… read more here.
Keywords: ldpc decoder; ldpc; fpga based; quasi cyclic ... See more keywords
A 5.28-Gb/s LDPC Decoder With Time-Domain Signal Processing for IEEE 802.15.3c Applications
Sign Up to like & getrecommendations! Published in 2017 at "IEEE Journal of Solid-State Circuits"
DOI: 10.1109/jssc.2016.2624983
Abstract: This paper presents a high-throughput, energy-efficient, and scalable low-density parity-check (LDPC) decoder with time-domain (TD) signal processing. The proposed arbiter-based minimum value finder is able to support practical long codes. The latency for determining the… read more here.
Keywords: ldpc decoder; processing; time domain; decoder time ... See more keywords
A 2.267-Gb/s, 93.7-pJ/bit Non-Binary LDPC Decoder With Logarithmic Quantization and Dual-Decoding Algorithm Scheme for Storage Applications
Sign Up to like & getrecommendations! Published in 2018 at "IEEE Journal of Solid-State Circuits"
DOI: 10.1109/jssc.2018.2832851
Abstract: Non-binary low-density parity-check (NB-LDPC) codes are a promising class of error-correcting codes that provide excellent coding gain beyond that of their binary counterparts. However, their decoding complexity has thus far limited practicality. We present an… read more here.
Keywords: ldpc decoder; logarithmic quantization; scheme; storage applications ... See more keywords
A High-Efficiency Segmented Reconfigurable Cyclic Shifter for 5G QC-LDPC Decoder
Sign Up to like & getrecommendations! Published in 2022 at "IEEE Transactions on Circuits and Systems I: Regular Papers"
DOI: 10.1109/tcsi.2021.3114395
Abstract: A reconfigurable cyclic shifter is a key element of a QC-LDPC decoder, which is crucial for 5G communication systems. If a traditional reconfigurable cyclic shifter can only shift one input of variable size at a… read more here.
Keywords: ldpc decoder; decoder; reconfigurable cyclic; cyclic shifter ... See more keywords
Parallel and Flexible 5G LDPC Decoder Architecture Targeting FPGA
Sign Up to like & getrecommendations! Published in 2021 at "IEEE Transactions on Very Large Scale Integration (VLSI) Systems"
DOI: 10.1109/tvlsi.2021.3072866
Abstract: The quasi-cyclic (QC) low-density parity-check (LDPC) code is a key error correction code for the fifth generation (5G) of cellular network technology. Designed to support several frame sizes and code rates, the 5G LDPC code… read more here.
Keywords: parallel flexible; processing rate; architecture; rate ... See more keywords
Low Power QC-LDPC Decoder Based on Token Ring Architecture
Sign Up to like & getrecommendations! Published in 2020 at "Energies"
DOI: 10.3390/en13236310
Abstract: The article presents an implementation of a low power Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) decoder in a Field Programmable Gate Array (FPGA) device. The proposed solution is oriented to a reduction in dynamic energy consumption. The… read more here.
Keywords: ldpc decoder; low power; token ring; architecture ... See more keywords