Model-Based Design of Flexible and Efficient LDPC Decoders on FPGA Devices
Sign Up to like & getrecommendations! Published in 2020 at "Journal of Signal Processing Systems"
DOI: 10.1007/s11265-020-01519-0
Abstract: Advances in digital communication advocate for the use of hardware LDPC decoders in applications requiring reliable and fast information transfer. Hand-coded RTL architectures provide the highest performances but slower the path to IP design. By… read more here.
Keywords: based design; ldpc; ldpc decoders; model based ... See more keywords
A Universal Efficient Circular-Shift Network for Reconfigurable Quasi-Cyclic LDPC Decoders
Sign Up to like & getrecommendations! Published in 2022 at "IEEE Transactions on Very Large Scale Integration (VLSI) Systems"
DOI: 10.1109/tvlsi.2022.3190317
Abstract: Quasi-cyclic low-density parity-check (QC-LDPC) codes for modern communication standards usually have multiple code rates and block lengths. Therefore, reconfigurable LDPC decoders have received widespread attention, which require circular-shift networks to support various expansion factors. Besides,… read more here.
Keywords: network; ldpc decoders; shift; quasi cyclic ... See more keywords