Study of 3-D Line Edge Roughness (LER) in Vertical Channel Array Transistor for DRAM
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DOI: 10.1109/tcad.2025.3546195
Abstract: Line edge roughness (LER) is an undesirable phenomenon that arises during semiconductor fabrication processes, causing fluctuations in the characteristics of semiconductor devices and potentially leading to significant yield degradation. Consequently, LER must be meticulously considered… read more here.
Keywords: ler; transistor; ler vertical; line edge ... See more keywords