High performance suspended spiral inductor and band-pass filter by wafer level packaging technology
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DOI: 10.1007/s00542-016-2977-1
Abstract: Suspended inductors and 2.45 GHz BPF with patterned ground shields on the lossy silicon substrate by using Cu/BCB based wafer level packaging and bulk Si etching technologies were fabricated. Thick BCB interlayer is used as the… read more here.
Keywords: wafer level; level packaging; band; pass ... See more keywords
Warpage and Thermal Characterization of Fan-Out Wafer-Level Packaging
Sign Up to like & getrecommendations! Published in 2017 at "IEEE Transactions on Components, Packaging and Manufacturing Technology"
DOI: 10.1109/ectc.2017.309
Abstract: In this paper, the warpage and thermal performances of fan-out wafer-level packaging (FOWLP) are investigated. Emphasis is placed on the characterization of the effects of FOWLP important parameters, such as chip size, chip thickness, package/chip… read more here.
Keywords: wafer level; level packaging; warpage thermal; warpage ... See more keywords
Chip-First Fan-Out Panel-Level Packaging for Heterogeneous Integration
Sign Up to like & getrecommendations! Published in 2018 at "IEEE Transactions on Components, Packaging and Manufacturing Technology"
DOI: 10.1109/tcpmt.2018.2848665
Abstract: The design, materials, process, fabrication, and reliability of a heterogeneous integration of four chips by a fan-out panel-level packaging (FOPLP) method are investigated in this paper. Emphasis is placed on the application of a special… read more here.
Keywords: panel level; heterogeneous integration; level packaging; fan panel ... See more keywords
Thermomechanical Oriented Reliability Enhancement of Si MOSFET Panel-Level Packaging Fusing Ant Colony Optimization With Backpropagation Neural Network
Sign Up to like & getrecommendations! Published in 2023 at "IEEE Transactions on Components, Packaging and Manufacturing Technology"
DOI: 10.1109/tcpmt.2023.3267411
Abstract: Considerable advancements in power semiconductor devices have resulted in such devices being increasingly adopted in applications of energy generation, conversion, and transmission. Hence, we proposed a fan-out panel-level packaging (FOPLP) design for 30-V Si-based metal–oxide–semiconductor… read more here.
Keywords: ant colony; packaging; reliability; panel level ... See more keywords
The Mathematical Model and Novel Final Test System for Wafer-Level Packaging
Sign Up to like & getrecommendations! Published in 2017 at "IEEE Transactions on Industrial Informatics"
DOI: 10.1109/tii.2016.2643694
Abstract: To develop integrated circuit (IC) test of wafer-level packaging, the electromechanical model of microprobe testing process and the IC final test system of wafer-level packaging based on microprobe arrays are first proposed. An electromechanical model… read more here.
Keywords: wafer level; level packaging; system; test ... See more keywords