Aging-aware scheduling and binding in high-level synthesis considering workload effects
Sign Up to like & getrecommendations! Published in 2020 at "Microelectronics Reliability"
DOI: 10.1016/j.microrel.2019.113549
Abstract: Abstract Transistor aging is a major reliability concern in nanoscale digital design, and addressing it during high-level synthesis (HLS) is essential to enhance the lifetime of circuits. Motivated by exploring workload effects on aging, we… read more here.
Keywords: workload effects; effects aging; high level; level synthesis ... See more keywords
SpecHLS: Speculative Accelerator Design Using High-Level Synthesis
Sign Up to like & getrecommendations! Published in 2022 at "IEEE Micro"
DOI: 10.1109/mm.2022.3188136
Abstract: Custom hardware accelerators usage is shifting toward new application domains such as graph analytics and unstructured text analysis. These applications expose complex control-flow which is challenging to map to hardware, especially when operating from a… read more here.
Keywords: using high; level synthesis; synthesis; spechls speculative ... See more keywords
Svelto: High-Level Synthesis of Multi-Threaded Accelerators for Graph Analytics
Sign Up to like & getrecommendations! Published in 2022 at "IEEE Transactions on Computers"
DOI: 10.1109/tc.2021.3057860
Abstract: Graph analytics are an emerging class of irregular applications. Operating on very large datasets, they present unique behaviors, such as fine-grained, unpredictable memory accesses, and highly unbalanced task level parallelism, that make existing high-performance general-purpose… read more here.
Keywords: level; level synthesis; accelerators graph; graph analytics ... See more keywords
Performance Modeling and Directives Optimization for High-Level Synthesis on FPGA
Sign Up to like & getrecommendations! Published in 2020 at "IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"
DOI: 10.1109/tcad.2019.2912916
Abstract: High-level synthesis (HLS) relies on the use of synthesis directives to generate digital designs meeting a set of specifications. However, the selection of directives depends largely on designer experience and knowledge of the target architecture… read more here.
Keywords: synthesis; performance; level synthesis; design ... See more keywords
A Streaming Dataflow Engine for Sparse Matrix-Vector Multiplication Using High-Level Synthesis
Sign Up to like & getrecommendations! Published in 2020 at "IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"
DOI: 10.1109/tcad.2019.2912923
Abstract: Using high-level synthesis techniques, this paper proposes an adaptable high-performance streaming dataflow engine for sparse matrix dense vector multiplication (SpMV) suitable for embedded FPGAs. As the SpMV is a memory-bound algorithm, this engine combines the… read more here.
Keywords: vector; level synthesis; engine; average factor ... See more keywords
FastSim: A Fast Simulation Framework for High-Level Synthesis
Sign Up to like & getrecommendations! Published in 2022 at "IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"
DOI: 10.1109/tcad.2021.3090339
Abstract: High-level synthesis (HLS) is a well-established framework used to translate high-level algorithmic behaviors into hardware designs. Despite the enduring research efforts, a major prevailing bottleneck of HLS is the large gap between the design and… read more here.
Keywords: level; level synthesis; simulation; design ... See more keywords
BLAST: Belling the Black-Hat High-Level Synthesis Tool
Sign Up to like & getrecommendations! Published in 2022 at "IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"
DOI: 10.1109/tcad.2022.3200513
Abstract: A hardware Trojan (HT) is a malicious modification of the design done by a rogue employee or a malicious foundry to leak secret information, create a backdoor for attackers, alter functionality, degrade performance and even… read more here.
Keywords: tool; level synthesis; black hat; level ... See more keywords
Hybrid sorting algorithm implemented by High Level Synthesis
Sign Up to like & getrecommendations! Published in 2019 at "IEEE Latin America Transactions"
DOI: 10.1109/tla.2019.9082258
Abstract: This paper proposes a hybrid data ordering algorithm which executes serial and parallel instructions. The implementation of the system is presented in the Zedboard development board of Xilinx that includes a SoC (System on Chip).… read more here.
Keywords: hybrid sorting; level synthesis; algorithm; high level ... See more keywords
Transformations of High-Level Synthesis Codes for High-Performance Computing
Sign Up to like & getrecommendations! Published in 2021 at "IEEE Transactions on Parallel and Distributed Systems"
DOI: 10.1109/tpds.2020.3039409
Abstract: Spatial computing architectures promise a major stride in performance and energy efficiency over the traditional load/store devices currently employed in large scale computing systems. The adoption of high-level synthesis (HLS) from languages such as C++… read more here.
Keywords: performance computing; performance; high performance; level synthesis ... See more keywords
Verification of Scheduling of Conditional Behaviors in High-Level Synthesis
Sign Up to like & getrecommendations! Published in 2020 at "IEEE Transactions on Very Large Scale Integration (VLSI) Systems"
DOI: 10.1109/tvlsi.2020.2978242
Abstract: High-level synthesis (HLS) technique translates the behaviors written in high-level languages like C/C++ into register transfer level (RTL) design. Due to its complexity, proving the correctness of an HLS tool is prohibitively expensive. Translation validation… read more here.
Keywords: method; level; verification scheduling; level synthesis ... See more keywords