Self-Limited Low-Temperature Trimming and Fully Silicided S/D for Vertically Stacked Cantilever Gate-All-Around Poly-Si Junctionless Nanosheet Transistors
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DOI: 10.1109/jeds.2019.2940606
Abstract: A self-limited low-temperature trimming process is demonstrated without surface morphology degradation. It shows great potential to control the trimming process with a large process window (400–900 s). Subthreshold characteristics are improved and Ioff is drastically… read more here.
Keywords: sub; limited low; low temperature; self limited ... See more keywords