Ultra-Low Power CMOS Image Sensor With Two-Step Logical Shift Algorithm-Based Correlated Double Sampling Scheme
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DOI: 10.1109/tcsi.2020.3012980
Abstract: This article presents an ultra-low power counter structure for a column-parallel single-slope analog-to-digital converter (SS-ADC) in CMOS image sensors. The proposed counter employs a two-step logical shift algorithm-based correlated double sampling (CDS) scheme. The logical… read more here.
Keywords: power; two step; logical shift; cmos image ... See more keywords